From patchwork Thu Nov 6 15:50:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 31F481400A6 for ; Fri, 7 Nov 2014 02:52:26 +1100 (AEDT) Received: from localhost ([::1]:54561 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPMH-0002l6-4W for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 10:52:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLV-0001SK-6o for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLQ-0003vq-Qv for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:37 -0500 Received: from mail-pd0-f174.google.com ([209.85.192.174]:49464) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLQ-0003vh-Jb for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:32 -0500 Received: by mail-pd0-f174.google.com with SMTP id p10so1358742pdj.5 for ; Thu, 06 Nov 2014 07:51:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LnZYbeCKD9mFeF/zkR2RvDsx7vJgeyIw3VOIXcynbWo=; b=ERYuZYTqG2JjPM6Url5y4EI+givkv9Y4uEoPACFVF7cGZ/QUxEBo3UsIZvLvF02DPZ uGZhEfaJAeEBGytniZ0eRaFXsj6lmGWlASgXR1hJx/M2xoarUIfPiDEwILDUZtrNwqqa LD117Ap4q5uIn9Hu69vfe7pFnwuCvan0bSE51ituTXrONnNhnsuKchLIF/lk+PoDhp6z G/qxEVfWDeqvS/m2Z1F4ksMi3x/6EdtAssW0FPqnRumJjq/DVT9QmbOYBjhZrH4ua9G+ 9xPyrIXtJtB99ZNxio5yyT1irt9SbuL2iVk8I6cIPJAUko7lrSKQXfDbqjdjh3E7ocoO Dfaw== X-Gm-Message-State: ALoCoQk5O4HW/KCrAnPm8mxpmySHSfUeGMd/HorKcc23Pu26EWIxoIpX9AXQ+rkSRzbChicuyxvl X-Received: by 10.70.128.11 with SMTP id nk11mr5087614pdb.113.1415289091853; Thu, 06 Nov 2014 07:51:31 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.51.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:51:30 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:50:51 -0600 Message-Id: <1415289073-14681-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.174 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 04/26] target-arm: add non-secure Translation Block flag X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Sergey Fedorov This patch is based on idea found in patch at git://github.com/jowinter/qemu-trustzone.git f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by Johannes Winter . The TBFLAG captures the SCR NS secure state at the time when a TB is created so the correct bank is accessed on system register accesses. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Moved and renamed use_secure_reg() to this patch. New name is access_secure_reg(). - Fixed function comment v5 -> v6 - Removed 64-bit NS TBFLAG macros as they are not needed - Added comment on DisasContext ns field - Replaced use of USE_SECURE_REG with use_secure_reg v4 -> v5 - Merge changes - Fixed issue where TB secure state flag was incorrectly being set based on secure state rather than NS setting. This caused an issue where monitor mode MRC/MCR accesses were always secure rather than being based on NS bit setting. - Added separate 64/32 TB secure state flags - Unconditionalized the setting of the DC ns bit - Removed IS_NS macro and replaced with direct usage. --- target-arm/cpu.h | 27 +++++++++++++++++++++++++++ target-arm/translate.c | 1 + target-arm/translate.h | 1 + 3 files changed, 29 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7769ccf..69aed3e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -817,6 +817,22 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Function for determing whether guest cp register reads and writes should + * access the secure or non-secure bank of a cp register. When EL3 is + * operating in AArch32 state, the NS-bit determines whether the secure + * instance of a cp register should be used. When EL3 is AArch64 (or if + * it doesn't exist at all) then there is no register banking, and all + * accesses are to the non-secure version. + */ +static inline bool access_secure_reg(CPUARMState *env) +{ + bool ret = (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && + !(env->cp15.scr_el3 & SCR_NS)); + + return ret; +} + /* Macros for accessing a specified CP register bank */ #define A32_BANKED_REG_GET(_env, _regname, _secure) \ ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) @@ -1467,6 +1483,12 @@ static inline bool arm_singlestep_active(CPUARMState *env) */ #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) +/* Indicates whether cp register reads and writes by guest code should access + * the secure or nonsecure bank of banked registers; note that this is not + * the same thing as the current security state of the processor! + */ +#define ARM_TBFLAG_NS_SHIFT 22 +#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state */ #define ARM_TBFLAG_AA64_EL_SHIFT 0 @@ -1511,6 +1533,8 @@ static inline bool arm_singlestep_active(CPUARMState *env) (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT) #define ARM_TBFLAG_AA64_PSTATE_SS(F) \ (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT) +#define ARM_TBFLAG_NS(F) \ + (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -1560,6 +1584,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (privmode) { *flags |= ARM_TBFLAG_PRIV_MASK; } + if (!(access_secure_reg(env))) { + *flags |= ARM_TBFLAG_NS_MASK; + } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { *flags |= ARM_TBFLAG_VFPEN_MASK; diff --git a/target-arm/translate.c b/target-arm/translate.c index af51568..17c459a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11031,6 +11031,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, #if !defined(CONFIG_USER_ONLY) dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); #endif + dc->ns = ARM_TBFLAG_NS(tb->flags); dc->cpacr_fpen = ARM_TBFLAG_CPACR_FPEN(tb->flags); dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); diff --git a/target-arm/translate.h b/target-arm/translate.h index 41a9071..f6ee789 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -20,6 +20,7 @@ typedef struct DisasContext { #if !defined(CONFIG_USER_ONLY) int user; #endif + bool ns; /* Use non-secure CPREG bank on access */ bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len;