From patchwork Wed Aug 13 21:56:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Snow X-Patchwork-Id: 379759 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 730FC14009B for ; Thu, 14 Aug 2014 07:59:30 +1000 (EST) Received: from localhost ([::1]:50491 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHgZs-0006gq-MO for incoming@patchwork.ozlabs.org; Wed, 13 Aug 2014 17:59:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37231) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHgXE-00026M-Ou for qemu-devel@nongnu.org; Wed, 13 Aug 2014 17:56:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XHgX8-0000Xx-2u for qemu-devel@nongnu.org; Wed, 13 Aug 2014 17:56:44 -0400 Received: from mx1.redhat.com ([209.132.183.28]:1108) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XHgX7-0000Xt-RR for qemu-devel@nongnu.org; Wed, 13 Aug 2014 17:56:38 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s7DLubjM015003 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 13 Aug 2014 17:56:37 -0400 Received: from dhcp-17-12.bos.redhat.com ([10.18.17.175]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id s7DLuRRj017042; Wed, 13 Aug 2014 17:56:36 -0400 From: John Snow To: qemu-devel@nongnu.org Date: Wed, 13 Aug 2014 17:56:11 -0400 Message-Id: <1407966975-3723-5-git-send-email-jsnow@redhat.com> In-Reply-To: <1407966975-3723-1-git-send-email-jsnow@redhat.com> References: <1407966975-3723-1-git-send-email-jsnow@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: jsnow@redhat.com, armbru@redhat.com, stefanha@redhat.com, mst@redhat.com Subject: [Qemu-devel] [PATCH v3 28/32] ahci: add test_pci_enable to ahci-test. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds a test wherein we engage the PCI AHCI device and ensure that the memory region for the HBA functionality is now accessible. Under Q35 environments, additional PCI configuration is performed to ensure that the HBA functionality will become usable. Signed-off-by: John Snow --- tests/ahci-test.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ tests/libqos/pci.c | 6 ++++++ 2 files changed, 63 insertions(+) diff --git a/tests/ahci-test.c b/tests/ahci-test.c index 29ac0d0..0ca4a20 100644 --- a/tests/ahci-test.c +++ b/tests/ahci-test.c @@ -56,6 +56,7 @@ /*** Globals ***/ static QGuestAllocator *guest_malloc; static QPCIBus *pcibus; +static uint64_t barsize; static char tmp_path[] = "/tmp/qtest.XXXXXX"; static bool ahci_pedantic; static uint32_t ahci_fingerprint; @@ -66,6 +67,7 @@ static uint32_t ahci_fingerprint; /*** Function Declarations ***/ static QPCIDevice *get_ahci_device(void); +static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base); static void free_ahci_device(QPCIDevice *dev); static void ahci_test_pci_spec(QPCIDevice *ahci); static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header, @@ -111,6 +113,9 @@ static void free_ahci_device(QPCIDevice *ahci) qpci_free_pc(pcibus); pcibus = NULL; } + + /* Clear our cached barsize information. */ + barsize = 0; } /*** Test Setup & Teardown ***/ @@ -169,6 +174,44 @@ static void ahci_shutdown(QPCIDevice *ahci) qtest_shutdown(); } +/*** Logical Device Initialization ***/ + +/** + * Start the PCI device and sanity-check default operation. + */ +static void ahci_pci_enable(QPCIDevice *ahci, void **hba_base) +{ + uint8_t reg; + + start_ahci_device(ahci, hba_base); + + switch(ahci_fingerprint) { + case AHCI_INTEL_ICH9: + /* ICH9 has a register at PCI 0x92 that + * acts as a master port enabler mask. */ + reg = qpci_config_readb(ahci, 0x92); + reg |= 0x3F; + qpci_config_writeb(ahci, 0x92, reg); + assert_bit_set(qpci_config_readb(ahci, 0x92), 0x3F); + break; + } + +} + +/** + * Map BAR5/ABAR, and engage the PCI device. + */ +static QPCIDevice *start_ahci_device(QPCIDevice *ahci, void **hba_base) +{ + /* Map AHCI's ABAR (BAR5) */ + *hba_base = qpci_iomap(ahci, 5, &barsize); + + /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */ + qpci_device_enable(ahci); + + return ahci; +} + /*** Specification Adherence Tests ***/ /** @@ -428,6 +471,19 @@ static void test_pci_spec(void) ahci_shutdown(ahci); } +/** + * Engage the PCI AHCI device and sanity check the response. + * Perform additional PCI config space bringup for the HBA. + */ +static void test_pci_enable(void) +{ + QPCIDevice *ahci; + void *hba_base; + ahci = ahci_boot(); + ahci_pci_enable(ahci, &hba_base); + ahci_shutdown(ahci); +} + /******************************************************************************/ int main(int argc, char **argv) @@ -479,6 +535,7 @@ int main(int argc, char **argv) /* Run the tests */ qtest_add_func("/ahci/sanity", test_sanity); qtest_add_func("/ahci/pci_spec", test_pci_spec); + qtest_add_func("/ahci/pci_enable", test_pci_enable); ret = g_test_run(); diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c index ce0b308..b244689 100644 --- a/tests/libqos/pci.c +++ b/tests/libqos/pci.c @@ -73,6 +73,12 @@ void qpci_device_enable(QPCIDevice *dev) cmd = qpci_config_readw(dev, PCI_COMMAND); cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; qpci_config_writew(dev, PCI_COMMAND, cmd); + + /* Verify the bits are now set. */ + cmd = qpci_config_readw(dev, PCI_COMMAND); + g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO); + g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY); + g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER); } uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)