From patchwork Mon Aug 4 17:38:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 376380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 905C3140092 for ; Tue, 5 Aug 2014 02:44:32 +1000 (EST) Received: from localhost ([::1]:53555 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XELN8-0004QW-QF for incoming@patchwork.ozlabs.org; Mon, 04 Aug 2014 12:44:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XELEN-00071y-LD for qemu-devel@nongnu.org; Mon, 04 Aug 2014 12:35:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XELEF-0002Hd-BE for qemu-devel@nongnu.org; Mon, 04 Aug 2014 12:35:27 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:19264) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XELEF-0002FW-0B for qemu-devel@nongnu.org; Mon, 04 Aug 2014 12:35:19 -0400 From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Mon, 4 Aug 2014 18:38:43 +0100 Message-Id: <1407173932-969-7-git-send-email-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1407173932-969-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1407173932-969-1-git-send-email-kbastian@mail.uni-paderborn.de> X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.1.1.2430161, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2014.8.4.162721 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 131.234.142.9 Cc: peter.maydell@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v3 06/15] target-tricore: Add instructions of SRC opcode format X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add instructions of SRC opcode format. Add micro-op generator functions for add, conditional add/sub and shi/shai. Signed-off-by: Bastian Koppelmann --- v2 -> v3: - Remove helper_shac, gen_shac - Remove len parameter of gen_shaci - Change gen_shaci to a special case. - Add gen_calc_psw_* functions to generate the calculation of PSW bits. - Add gen_add_i32 micro-op generator, that handles PSW bits. - Replace ADD instructions with gen_add_i32 for PSW bit calculation. - Change OP_COND to handle PSW bits. - MOV_A: Remove sign extended loading of const4 - gen_shi: Remove wrong documentation target-tricore/helper.h | 16 +++ target-tricore/translate.c | 244 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 260 insertions(+) -- 2.0.4 diff --git a/target-tricore/helper.h b/target-tricore/helper.h index e69de29..5884240 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 0d30c51..d1e6669 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -27,6 +27,7 @@ #include "exec/helper-gen.h" #include "tricore-opcodes.h" + /* * TCG registers */ @@ -102,8 +103,251 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, } +/* + * Functions to generate micro-ops + */ + +/* Functions for calculating PSW status bits */ + +static inline void gen_calc_psw_sv_i32(TCGv ret, TCGv arg) +{ + tcg_gen_xor_tl(ret, ret, arg); +} + +static inline void gen_calc_psw_av_i32(TCGv ret, TCGv arg) +{ + TCGv temp = tcg_temp_new(); + tcg_gen_muli_tl(temp, arg, 2); + tcg_gen_xor_tl(temp, arg, temp); + tcg_gen_andi_tl(ret, temp, 0x80000000); + tcg_temp_free(temp); +} + +static inline void gen_calc_psw_sav_i32(TCGv ret, TCGv arg) +{ + tcg_gen_xor_tl(ret, ret, arg); +} + +/* Functions for arithmetic instructions */ + +static inline void gen_add_i32(TCGv ret, TCGv r1, TCGv r2) +{ + TCGv t0 = tcg_temp_new_i32(); + /* Addition and set V/SV bits */ + tcg_gen_movi_tl(t0, 0); + tcg_gen_add2_tl(ret, cpu_PSW_V, r1, t0, r2, t0); + gen_calc_psw_sv_i32(cpu_PSW_SV, cpu_PSW_V); + /* Calc AV/SAV bits */ + gen_calc_psw_av_i32(cpu_PSW_AV, ret); + gen_calc_psw_sav_i32(cpu_PSW_SAV, cpu_PSW_AV); + tcg_temp_free(t0); +} + +static inline void gen_addi_i32(TCGv ret, TCGv r1, target_ulong r2) +{ + TCGv temp = tcg_const_i32(r2); + gen_add_i32(ret, r1, temp); + tcg_temp_free(temp); +} + +#define OP_COND(insn)\ +static inline void gen_cond_##insn(int cond, TCGv r1, TCGv r2, TCGv r3, \ + TCGv r4) \ +{ \ + TCGv temp = tcg_temp_new(); \ + TCGv temp2 = tcg_temp_new(); \ + TCGv t0 = tcg_const_i32(0); \ + \ + tcg_gen_##insn ## 2_tl(temp, temp2, r1, t0, r2, t0); \ + tcg_gen_movcond_tl(cond, r3, r4, t0, temp, r3); \ + /* Set PSW_V conditional */ \ + tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp2, cpu_PSW_V); \ + /* Set PSW_SV conditional */ \ + gen_calc_psw_sv_i32(temp2, cpu_PSW_SV); \ + tcg_gen_movcond_tl(cond, cpu_PSW_SV, r4, t0, temp2, cpu_PSW_SV); \ + /* calc AV bit */ \ + gen_calc_psw_av_i32(temp2, temp); \ + tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp2, cpu_PSW_AV); \ + /* calc SAV bit */ \ + gen_calc_psw_sav_i32(temp2, cpu_PSW_SAV); \ + tcg_gen_movcond_tl(cond, cpu_PSW_SAV, r4, t0, temp2, cpu_PSW_SAV); \ + \ + tcg_temp_free(t0); \ + tcg_temp_free(temp); \ + tcg_temp_free(temp2); \ +} \ + \ +static inline void gen_condi_##insn(int cond, TCGv r1, int32_t r2, \ + TCGv r3, TCGv r4) \ +{ \ + TCGv temp = tcg_const_i32(r2); \ + gen_cond_##insn(cond, r1, temp, r3, r4); \ + tcg_temp_free(temp); \ +} + +OP_COND(add) +OP_COND(sub) + +static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) +{ + if (shift_count == -32) { + tcg_gen_movi_tl(ret, 0); + } else if (shift_count >= 0) { + tcg_gen_shli_tl(ret, r1, shift_count); + } else { + tcg_gen_shri_tl(ret, r1, (-shift_count)); + } +} + +static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) +{ + uint32_t msk, msk_start; + TCGv_i64 temp = tcg_temp_new_i64(); + TCGv_i64 result = tcg_temp_new_i64(); + TCGv_i64 t_0 = tcg_const_i64(0); + TCGv_i64 t_1 = tcg_const_i64(1); + TCGv_i64 t_max = tcg_const_i64(0x7FFFFFFF); + TCGv_i64 t_min = tcg_const_i64(-(0x80000000L)); + + if (shift_count == 0) { + /* Clear PSW.C */ + tcg_gen_movi_tl(cpu_PSW_C, 0); + tcg_gen_mov_tl(ret, r1); + } else if (shift_count > 0) { + tcg_gen_ext_i32_i64(temp, r1); + tcg_gen_shli_i64(result, temp, shift_count); + /* calc carry */ + msk_start = 32 - shift_count; + msk = ((1 << shift_count) - 1) << msk_start; + tcg_gen_andi_tl(cpu_PSW_C, r1, msk); + } else { + tcg_gen_ext_i32_i64(temp, r1); + tcg_gen_sari_i64(result, temp, -(shift_count)); + /* calc carry */ + msk = (1 << (shift_count - 1)) - 1; + tcg_gen_andi_tl(cpu_PSW_C, r1, msk); + } + /* calc v/sv bits only if shift happened and write back 64bit result*/ + if (shift_count != 0) { + /* v/sv */ + tcg_gen_movcond_i64(TCG_COND_GT, temp, result, t_max, t_1, t_0); + tcg_gen_movcond_i64(TCG_COND_LT, temp, result, t_min, t_1, temp); + tcg_gen_trunc_i64_i32(cpu_PSW_V, temp); + + gen_calc_psw_sv_i32(cpu_PSW_SV, cpu_PSW_V); + /* write back result */ + tcg_gen_trunc_i64_i32(ret, result); + } + /* calc av overflow bit */ + gen_calc_psw_av_i32(cpu_PSW_AV, ret); + /* calc sav overflow bit */ + gen_calc_psw_sav_i32(cpu_PSW_SAV, cpu_PSW_AV); + + tcg_temp_free_i64(temp); + tcg_temp_free_i64(result); + tcg_temp_free_i64(t_0); + tcg_temp_free_i64(t_1); + tcg_temp_free_i64(t_max); + tcg_temp_free_i64(t_min); +} + +/* + * Functions for decoding instructions + */ + +static void decode_src_opc(DisasContext *ctx, int op1) +{ + int r1; + int32_t const4; + TCGv temp, temp2; + + r1 = MASK_OP_SRC_S1D(ctx->opcode); + const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); + + switch (op1) { + case OPC1_16_SRC_ADD: + gen_addi_i32(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); + break; + case OPC1_16_SRC_ADD_A15: + gen_addi_i32(cpu_gpr_d[15], cpu_gpr_d[r1], const4); + break; + case OPC1_16_SRC_ADD_15A: + gen_addi_i32(cpu_gpr_d[r1], cpu_gpr_d[15], const4); + break; + case OPC1_16_SRC_ADD_A: + gen_addi_i32(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); + break; + case OPC1_16_SRC_CADD: + gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], + cpu_gpr_d[15]); + break; + case OPC1_16_SRC_CADDN: + gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], + cpu_gpr_d[15]); + break; + case OPC1_16_SRC_CMOV: + temp = tcg_const_tl(0); + temp2 = tcg_const_tl(const4); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, + temp2, cpu_gpr_d[r1]); + tcg_temp_free(temp); + tcg_temp_free(temp2); + break; + case OPC1_16_SRC_CMOVN: + temp = tcg_const_tl(0); + temp2 = tcg_const_tl(const4); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, + temp2, cpu_gpr_d[r1]); + tcg_temp_free(temp); + tcg_temp_free(temp2); + break; + case OPC1_16_SRC_EQ: + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], + const4); + break; + case OPC1_16_SRC_LT: + tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], + const4); + break; + case OPC1_16_SRC_MOV: + tcg_gen_movi_tl(cpu_gpr_d[r1], const4); + break; + case OPC1_16_SRC_MOV_A: + tcg_gen_movi_tl(cpu_gpr_a[r1], const4); + break; + case OPC1_16_SRC_SH: + gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); + break; + case OPC1_16_SRC_SHA: + gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); + break; + } +} + static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) { + int op1; + + op1 = MASK_OP_MAJOR(ctx->opcode); + + switch (op1) { + case OPC1_16_SRC_ADD: + case OPC1_16_SRC_ADD_A15: + case OPC1_16_SRC_ADD_15A: + case OPC1_16_SRC_ADD_A: + case OPC1_16_SRC_CADD: + case OPC1_16_SRC_CADDN: + case OPC1_16_SRC_CMOV: + case OPC1_16_SRC_CMOVN: + case OPC1_16_SRC_EQ: + case OPC1_16_SRC_LT: + case OPC1_16_SRC_MOV: + case OPC1_16_SRC_MOV_A: + case OPC1_16_SRC_SH: + case OPC1_16_SRC_SHA: + decode_src_opc(ctx, op1); + break; + } } static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx)