From patchwork Mon Aug 4 17:38:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 376379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 12735140092 for ; Tue, 5 Aug 2014 02:43:35 +1000 (EST) Received: from localhost ([::1]:53546 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XELMD-00039p-8O for incoming@patchwork.ozlabs.org; Mon, 04 Aug 2014 12:43:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XELEL-00071d-6D for qemu-devel@nongnu.org; Mon, 04 Aug 2014 12:35:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XELEE-0002Gs-G7 for qemu-devel@nongnu.org; Mon, 04 Aug 2014 12:35:24 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:19261) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XELEE-0002FN-6E for qemu-devel@nongnu.org; Mon, 04 Aug 2014 12:35:18 -0400 From: Bastian Koppelmann To: qemu-devel@nongnu.org Date: Mon, 4 Aug 2014 18:38:41 +0100 Message-Id: <1407173932-969-5-git-send-email-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1407173932-969-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1407173932-969-1-git-send-email-kbastian@mail.uni-paderborn.de> X-IMT-Spam-Score: 0.0 () X-PMX-Version: 6.1.1.2430161, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2014.8.4.162721 X-IMT-Authenticated-Sender: uid=kbastian,ou=People,o=upb,c=de X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 131.234.142.9 Cc: peter.maydell@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [PATCH v3 04/15] target-tricore: Add initialization for translation and activate target X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add tcg and cpu model initialization. Add gen_intermediate_code function. Activate target in configure and add softmmu config. Signed-off-by: Bastian Koppelmann --- v2 -> v3: - Add initialization for PSW_USB bits as TCG regs. - Remove cpu_tricore_init from translate.c (see patch v3[01/15]) - Remove translate_init.c (see patch v3[01/15]) configure | 5 ++ default-configs/tricore-softmmu.mak | 3 + target-tricore/translate.c | 165 ++++++++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 default-configs/tricore-softmmu.mak -- 2.0.4 diff --git a/configure b/configure index f7685b5..5003e28 100755 --- a/configure +++ b/configure @@ -4965,6 +4965,9 @@ case "$target_name" in TARGET_BASE_ARCH=mips echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak ;; + tricore) + target_phys_bits=32 + ;; moxie) ;; or32) @@ -5162,6 +5165,8 @@ for i in $ARCH $TARGET_BASE_ARCH ; do echo "CONFIG_MIPS_DIS=y" >> $config_target_mak echo "CONFIG_MIPS_DIS=y" >> config-all-disas.mak ;; + tricore*) + ;; moxie*) echo "CONFIG_MOXIE_DIS=y" >> $config_target_mak echo "CONFIG_MOXIE_DIS=y" >> config-all-disas.mak diff --git a/default-configs/tricore-softmmu.mak b/default-configs/tricore-softmmu.mak new file mode 100644 index 0000000..48ccd12 --- /dev/null +++ b/default-configs/tricore-softmmu.mak @@ -0,0 +1,3 @@ +include pci.mak +CONFIG_PFLASH_CFI01=y +CONFIG_SMC91C111=y diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 5bb212d..7275c49 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -26,6 +26,26 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" +/* + * TCG registers + */ +static TCGv cpu_PC; +static TCGv cpu_PCXI; +static TCGv cpu_PSW; +static TCGv cpu_ICR; +/* GPR registers */ +static TCGv cpu_gpr_a[16]; +static TCGv cpu_gpr_d[16]; +/* PSW Flag cache */ +static TCGv cpu_PSW_C; +static TCGv cpu_PSW_V; +static TCGv cpu_PSW_SV; +static TCGv cpu_PSW_AV; +static TCGv cpu_PSW_SAV; +/* CPU env */ +static TCGv_ptr cpu_env; + +#include "exec/gen-icount.h" static const char *regnames_a[] = { "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , @@ -39,6 +59,25 @@ static const char *regnames_d[] = { "d12" , "d13" , "d14" , "d15", }; +typedef struct DisasContext { + struct TranslationBlock *tb; + target_ulong pc, saved_pc, next_pc; + uint32_t opcode; + int singlestep_enabled; + /* Routine used to access memory */ + int mem_idx; + uint32_t hflags, saved_hflags; + int bstate; +} DisasContext; + +enum { + + BS_NONE = 0, + BS_STOP = 1, + BS_BRANCH = 2, + BS_EXCP = 3, +}; + void tricore_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -62,10 +101,88 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, } +static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx) +{ +} + +static void decode_32Bit_opc(CPUTRICOREState *env, DisasContext *ctx) +{ +} + +static void decode_opc(CPUTRICOREState *env, DisasContext *ctx, int *is_branch) +{ + /* 16-Bit Instruction */ + if ((ctx->opcode & 0x1) == 0) { + ctx->next_pc = ctx->pc + 2; + decode_16Bit_opc(env, ctx); + /* 32-Bit Instruction */ + } else { + ctx->next_pc = ctx->pc + 4; + decode_32Bit_opc(env, ctx); + } +} + static inline void gen_intermediate_code_internal(TRICORECPU *cpu, struct TranslationBlock *tb, int search_pc) { + CPUState *cs = CPU(cpu); + CPUTRICOREState *env = &cpu->env; + DisasContext ctx; + target_ulong pc_start; + int num_insns; + uint16_t *gen_opc_end; + + if (search_pc) { + qemu_log("search pc %d\n", search_pc); + } + + num_insns = 0; + pc_start = tb->pc; + gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; + ctx.pc = pc_start; + ctx.saved_pc = -1; + ctx.tb = tb; + ctx.singlestep_enabled = cs->singlestep_enabled; + ctx.bstate = BS_NONE; + ctx.mem_idx = cpu_mmu_index(env); + + tcg_clear_temp_count(); + gen_tb_start(); + while (ctx.bstate == BS_NONE) { + ctx.opcode = cpu_ldl_code(env, ctx.pc); + decode_opc(env, &ctx, 0); + + num_insns++; + + ctx.pc = ctx.next_pc; + if (tcg_ctx.gen_opc_ptr >= gen_opc_end) { + break; + } + if (singlestep) { + break; + } + } + + gen_tb_end(tb, num_insns); + *tcg_ctx.gen_opc_ptr = INDEX_op_end; + if (search_pc) { + printf("done_generating search pc\n"); + } else { + tb->size = ctx.pc - pc_start; + tb->icount = num_insns; + } + if (tcg_check_temp_count()) { + printf("LEAK at %08x\n", env->PC); + } + +#ifdef DEBUG_DISAS + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { + qemu_log("IN: %s\n", lookup_symbol(pc_start)); + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); + qemu_log("\n"); + } +#endif } void @@ -93,8 +210,56 @@ restore_state_to_opc(CPUTRICOREState *env, TranslationBlock *tb, int pc_pos) void cpu_state_reset(CPUTRICOREState *env) { + /* Reset Regs to Default Value */ + env->PSW = 0xb80; +} + +static void tricore_tcg_init_csfr(void) +{ + cpu_PCXI = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PCXI), "PCXI"); + cpu_PSW = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PSW), "PSW"); + cpu_PC = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PC), "PC"); + cpu_ICR = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, ICR), "ICR"); } void tricore_tcg_init(void) { + int i; + static int inited; + if (inited) { + return; + } + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + /* reg init */ + for (i = 0 ; i < 16 ; i++) { + cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, gpr_a[i]), + regnames_a[i]); + } + for (i = 0 ; i < 16 ; i++) { + cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, gpr_d[i]), + regnames_d[i]); + } + tricore_tcg_init_csfr(); + /* init PSW flag cache */ + cpu_PSW_C = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PSW_USB_C), + "PSW_C"); + cpu_PSW_V = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PSW_USB_V), + "PSW_V"); + cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PSW_USB_SV), + "PSW_SV"); + cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PSW_USB_AV), + "PSW_AV"); + cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUTRICOREState, PSW_USB_SAV), + "PSW_SAV"); }