diff mbox

[v3,03/21] target-mips: add SELEQZ and SELNEZ instructions

Message ID 1403882530-47821-4-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae June 27, 2014, 3:21 p.m. UTC 
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
---
v2:
* correct conditions to match instruction name
---
 disas/mips.c            |    8 ++++++++
 target-mips/translate.c |   16 ++++++++++++++++
 2 files changed, 24 insertions(+), 0 deletions(-)

Comments

James Hogan Sept. 26, 2014, 12:03 p.m. UTC | #1 
Hi Leon,

On 27/06/14 16:21, Leon Alrae wrote:
>  /* MIPS64 MIPS-3D ASE support.  */
>  #define I16     INSN_MIPS16
> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>     them first.  The assemblers uses a hash table based on the
>     instruction name anyhow.  */
>  /* name,    args,	match,	    mask,	pinfo,          	membership */
> +{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
> +{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},

I don't think these need to be at the beginning of the table since
they're normal instructions, unlike "nop" for example which is encoded
as a "sll".

Otherwise
Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James
James Hogan Sept. 26, 2014, 12:23 p.m. UTC | #2 
Hi Leon,

On 27/06/14 16:21, Leon Alrae wrote:
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 931a580..bb95f7b 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -189,6 +189,9 @@ enum {
>      OPC_MOVZ     = 0x0A | OPC_SPECIAL,
>      OPC_MOVN     = 0x0B | OPC_SPECIAL,
>  
> +    OPC_SELEQZ   = 0x35 | OPC_SPECIAL,
> +    OPC_SELNEZ   = 0x37 | OPC_SPECIAL,
> +
>      OPC_MOVCI    = 0x01 | OPC_SPECIAL,
>  
>      /* Special */

maybe it makes sense to remove OPC_SPECIAL35_RESERVED and
OPC_SPECIAL37_RESERVED now too.

Cheers
James
Leon Alrae Sept. 26, 2014, 12:45 p.m. UTC | #3 
Hi James,

On 26/09/2014 13:03, James Hogan wrote:
> Hi Leon,
> 
> On 27/06/14 16:21, Leon Alrae wrote:
>>  /* MIPS64 MIPS-3D ASE support.  */
>>  #define I16     INSN_MIPS16
>> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>>     them first.  The assemblers uses a hash table based on the
>>     instruction name anyhow.  */
>>  /* name,    args,	match,	    mask,	pinfo,          	membership */
>> +{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
>> +{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
> 
> I don't think these need to be at the beginning of the table since
> they're normal instructions, unlike "nop" for example which is encoded
> as a "sll".

I don't have any preference on this, just wanted to have new R6
instructions grouped. As I can see in binutils new R6 instructions were
placed at the bottom so I could stick to it as well.

Thanks,
Leon
James Hogan Sept. 26, 2014, 12:54 p.m. UTC | #4 
On 26/09/14 13:45, Leon Alrae wrote:
> Hi James,
> 
> On 26/09/2014 13:03, James Hogan wrote:
>> Hi Leon,
>>
>> On 27/06/14 16:21, Leon Alrae wrote:
>>>  /* MIPS64 MIPS-3D ASE support.  */
>>>  #define I16     INSN_MIPS16
>>> @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>>>     them first.  The assemblers uses a hash table based on the
>>>     instruction name anyhow.  */
>>>  /* name,    args,	match,	    mask,	pinfo,          	membership */
>>> +{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
>>> +{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
>>
>> I don't think these need to be at the beginning of the table since
>> they're normal instructions, unlike "nop" for example which is encoded
>> as a "sll".
> 
> I don't have any preference on this, just wanted to have new R6
> instructions grouped. As I can see in binutils new R6 instructions were
> placed at the bottom so I could stick to it as well.

It just seems like most of them are alphabetical in the main group, the
few at the top before "abs" seem to be specifically aliases of other
instructions, and the other groups at the bottom are there for specific
reasons too by the looks of it.

It's not my code though so if others are fine with it, so be it.

Cheers
James
diff mbox

Patch

diff --git a/disas/mips.c b/disas/mips.c
index 2106b57..b950e53 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -521,6 +521,8 @@  struct mips_opcode
 #define INSN_ISA64                0x00000040
 #define INSN_ISA32R2              0x00000080
 #define INSN_ISA64R2              0x00000100
+#define INSN_ISA32R6              0x00000200
+#define INSN_ISA64R6              0x00000400
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK		  0x0000f000
@@ -585,6 +587,8 @@  struct mips_opcode
 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 
+#define       ISA_MIPS32R6    (ISA_MIPS32R2 | INSN_ISA32R6)
+#define       ISA_MIPS64R6    (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
@@ -1121,6 +1125,8 @@  extern const int bfd_mips16_num_opcodes;
 #define I64     INSN_ISA64
 #define I33	INSN_ISA32R2
 #define I65	INSN_ISA64R2
+#define I32R6   INSN_ISA32R6
+#define I64R6   INSN_ISA64R6
 
 /* MIPS64 MIPS-3D ASE support.  */
 #define I16     INSN_MIPS16
@@ -1209,6 +1215,8 @@  const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,    args,	match,	    mask,	pinfo,          	membership */
+{"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
+{"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	0,		I4|I32|G3	},
 {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t,		0,		I4|I33	},
 {"nop",     "",         0x00000000, 0xffffffff, 0,              	INSN2_ALIAS,	I1      }, /* sll */
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 931a580..bb95f7b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -189,6 +189,9 @@  enum {
     OPC_MOVZ     = 0x0A | OPC_SPECIAL,
     OPC_MOVN     = 0x0B | OPC_SPECIAL,
 
+    OPC_SELEQZ   = 0x35 | OPC_SPECIAL,
+    OPC_SELNEZ   = 0x37 | OPC_SPECIAL,
+
     OPC_MOVCI    = 0x01 | OPC_SPECIAL,
 
     /* Special */
@@ -2408,6 +2411,14 @@  static void gen_cond_move(DisasContext *ctx, uint32_t opc,
         tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
         opn = "movz";
         break;
+    case OPC_SELNEZ:
+        tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
+        opn = "selnez";
+        break;
+    case OPC_SELEQZ:
+        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
+        opn = "seleqz";
+        break;
     }
     tcg_temp_free(t2);
     tcg_temp_free(t1);
@@ -14529,6 +14540,11 @@  static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
                                  INSN_LOONGSON2E | INSN_LOONGSON2F);
             gen_cond_move(ctx, op1, rd, rs, rt);
             break;
+        case OPC_SELEQZ:
+        case OPC_SELNEZ:
+            check_insn(ctx, ISA_MIPS32R6);
+            gen_cond_move(ctx, op1, rd, rs, rt);
+            break;
         case OPC_ADD ... OPC_SUBU:
             gen_arith(ctx, op1, rd, rs, rt);
             break;