From patchwork Wed Jun 11 15:19:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leon Alrae X-Patchwork-Id: 358761 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BE10D140076 for ; Thu, 12 Jun 2014 01:33:46 +1000 (EST) Received: from localhost ([::1]:47347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WukX2-0005Ba-OJ for incoming@patchwork.ozlabs.org; Wed, 11 Jun 2014 11:33:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WukKv-0001fA-Ta for qemu-devel@nongnu.org; Wed, 11 Jun 2014 11:21:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WukKq-0004B0-Ph for qemu-devel@nongnu.org; Wed, 11 Jun 2014 11:21:13 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:26703) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WukKq-0004Ad-KN for qemu-devel@nongnu.org; Wed, 11 Jun 2014 11:21:08 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 44EAB10746227; Wed, 11 Jun 2014 16:21:04 +0100 (IST) Received: from localhost.localdomain (192.168.14.85) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.181.6; Wed, 11 Jun 2014 16:21:06 +0100 From: Leon Alrae To: Date: Wed, 11 Jun 2014 16:19:51 +0100 Message-ID: <1402499992-64851-22-git-send-email-leon.alrae@imgtec.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> References: <1402499992-64851-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.14.85] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 195.59.15.196 Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net Subject: [Qemu-devel] [PATCH v2 21/22] target-mips: use pointers referring to appropriate decoding function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org After selecting CPU in QEMU the base ISA will not change. Therefore introducing *_arch function pointers that are set in cpu_state_reset to point at the appropriate SPECIAL and SPECIAL3 decoding functions, and avoid unnecessary 'if' statements. Signed-off-by: Leon Alrae --- target-mips/translate.c | 32 +++++++++++++++++++++----------- 1 files changed, 21 insertions(+), 11 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index de35b77..7ff7829 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15634,6 +15634,13 @@ out: tcg_temp_free(t1); } +/* Some instructions from MIPS32R6 and pre-MIPS32R6 have identical encoding. + + decode_opc_*_arch are pointing at the appropriate decoding functions + depending on a base ISA supported by selected MIPS CPU. */ +static void (*decode_opc_special_arch) (CPUMIPSState*, DisasContext*); +static void (*decode_opc_special3_arch) (CPUMIPSState*, DisasContext*); + static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; @@ -16002,11 +16009,8 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) break; #endif default: - if (ctx->insn_flags & ISA_MIPS32R6) { - decode_opc_special_r6(env, ctx); - } else { - decode_opc_special_legacy(env, ctx); - } + decode_opc_special_arch(env, ctx); + break; } } @@ -16799,12 +16803,9 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) tcg_temp_free(t0); } break; - default: /* Invalid */ - if (ctx->insn_flags & ISA_MIPS32R6) { - decode_opc_special3_r6(env, ctx); - } else { - decode_opc_special3_legacy(env, ctx); - } + default: + decode_opc_special3_arch(env, ctx); + break; } } @@ -17831,6 +17832,15 @@ void cpu_state_reset(CPUMIPSState *env) env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; env->insn_flags = env->cpu_model->insn_flags; + /* Select decoding functions appropriate for supported ISA */ + if (env->insn_flags & ISA_MIPS32R6) { + decode_opc_special_arch = decode_opc_special_r6; + decode_opc_special3_arch = decode_opc_special3_r6; + } else { + decode_opc_special_arch = decode_opc_special_legacy; + decode_opc_special3_arch = decode_opc_special3_legacy; + } + #if defined(CONFIG_USER_ONLY) env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); # ifdef TARGET_MIPS64