From patchwork Tue Jun 10 23:54:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabian Aggeler X-Patchwork-Id: 358436 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2F640140076 for ; Wed, 11 Jun 2014 10:00:06 +1000 (EST) Received: from localhost ([::1]:42552 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVxU-0005Qs-6G for incoming@patchwork.ozlabs.org; Tue, 10 Jun 2014 20:00:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38691) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVtE-0007YA-59 for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WuVt7-0004Cp-2g for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:40 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:14827) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WuVt6-0004CS-Te for qemu-devel@nongnu.org; Tue, 10 Jun 2014 19:55:33 -0400 Received: from CAS20.d.ethz.ch (172.31.51.110) by edge10.ethz.ch (82.130.75.186) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 11 Jun 2014 01:55:29 +0200 Received: from qemubox.ethz.ch (129.132.211.172) by CAS20.d.ethz.ch (172.31.51.110) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 11 Jun 2014 01:55:31 +0200 From: Fabian Aggeler To: Date: Wed, 11 Jun 2014 01:54:55 +0200 Message-ID: <1402444514-19658-14-git-send-email-aggelerf@ethz.ch> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 X-Originating-IP: [129.132.211.172] X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 82.130.75.186 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, greg.bellows@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, christoffer.dall@linaro.org Subject: [Qemu-devel] [PATCH v3 13/32] target-arm: implement IRQ/FIQ routing to Monitor mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index b9b458e..2fbecfa 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3705,12 +3705,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: