From patchwork Sat May 24 17:57:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 352151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AD62F140083 for ; Sun, 25 May 2014 04:00:35 +1000 (EST) Received: from localhost ([::1]:48943 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoGFF-0001Pr-D6 for incoming@patchwork.ozlabs.org; Sat, 24 May 2014 14:00:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37170) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoGDA-0005c7-EV for qemu-devel@nongnu.org; Sat, 24 May 2014 13:58:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoGD2-0006wk-GE for qemu-devel@nongnu.org; Sat, 24 May 2014 13:58:24 -0400 Received: from ssl.serverraum.org ([88.198.40.39]:40824) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoGD2-0006vr-7f for qemu-devel@nongnu.org; Sat, 24 May 2014 13:58:16 -0400 Received: from localhost (localhost [127.0.0.1]) by ssl.serverraum.org (Postfix) with ESMTP id A320D3F0EF; Sat, 24 May 2014 19:58:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at ssl.serverraum.org Received: from ssl.serverraum.org ([127.0.0.1]) by localhost (ssl.serverraum.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jyVDgjY3RuJw; Sat, 24 May 2014 19:58:13 +0200 (CEST) Received: from thanatos.fritz.box (91-67-172-82-dynip.superkabel.de [91.67.172.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 378C23F0F1; Sat, 24 May 2014 19:58:13 +0200 (CEST) From: Michael Walle To: qemu-devel@nongnu.org Date: Sat, 24 May 2014 19:57:50 +0200 Message-Id: <1400954270-12986-5-git-send-email-michael@walle.cc> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1400954270-12986-1-git-send-email-michael@walle.cc> References: <1400954270-12986-1-git-send-email-michael@walle.cc> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 88.198.40.39 Cc: Peter Maydell , Michael Walle Subject: [Qemu-devel] [PULL 4/4] lm32: remove lm32_sys X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since we have now semihosting on the lm32 target, this device is no longer needed. Remove it. Signed-off-by: Michael Walle --- hw/misc/Makefile.objs | 1 - hw/misc/lm32_sys.c | 179 ------------------------------------------------- target-lm32/README | 10 --- trace-events | 3 - 4 files changed, 193 deletions(-) delete mode 100644 hw/misc/lm32_sys.c diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index f674365..979e532 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -29,7 +29,6 @@ obj-$(CONFIG_NSERIES) += cbus.o obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o obj-$(CONFIG_IMX) += imx_ccm.o -obj-$(CONFIG_LM32) += lm32_sys.o obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o obj-$(CONFIG_MAINSTONE) += mst_fpga.o diff --git a/hw/misc/lm32_sys.c b/hw/misc/lm32_sys.c deleted file mode 100644 index 778eb6e..0000000 --- a/hw/misc/lm32_sys.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * QEMU model of the LatticeMico32 system control block. - * - * Copyright (c) 2010 Michael Walle - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -/* - * This model is mainly intended for testing purposes and doesn't fit to any - * real hardware. On the one hand it provides a control register (R_CTRL) on - * the other hand it supports the lm32 tests. - * - * A write to the control register causes a system shutdown. - * Tests first write the pointer to a test name to the test name register - * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if - * the test is passed or any non-zero value to it if the test is failed. - */ - -#include "hw/hw.h" -#include "hw/sysbus.h" -#include "trace.h" -#include "qemu/log.h" -#include "qemu/error-report.h" -#include "sysemu/sysemu.h" - -enum { - R_CTRL = 0, - R_PASSFAIL, - R_TESTNAME, - R_MAX -}; - -#define MAX_TESTNAME_LEN 32 - -#define TYPE_LM32_SYS "lm32-sys" -#define LM32_SYS(obj) OBJECT_CHECK(LM32SysState, (obj), TYPE_LM32_SYS) - -struct LM32SysState { - SysBusDevice parent_obj; - - MemoryRegion iomem; - uint32_t base; - uint32_t regs[R_MAX]; - uint8_t testname[MAX_TESTNAME_LEN]; -}; -typedef struct LM32SysState LM32SysState; - -static void copy_testname(LM32SysState *s) -{ - cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname, - MAX_TESTNAME_LEN); - s->testname[MAX_TESTNAME_LEN - 1] = '\0'; -} - -static void sys_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) -{ - LM32SysState *s = opaque; - char *testname; - - trace_lm32_sys_memory_write(addr, value); - - addr >>= 2; - switch (addr) { - case R_CTRL: - qemu_system_shutdown_request(); - break; - case R_PASSFAIL: - s->regs[addr] = value; - testname = (char *)s->testname; - fprintf(stderr, "TC %-*s %s\n", MAX_TESTNAME_LEN, - testname, (value) ? "FAILED" : "OK"); - if (value) { - cpu_dump_state(qemu_get_cpu(0), stderr, fprintf, 0); - } - break; - case R_TESTNAME: - s->regs[addr] = value; - copy_testname(s); - break; - - default: - error_report("lm32_sys: write access to unknown register 0x" - TARGET_FMT_plx, addr << 2); - break; - } -} - -static bool sys_ops_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write) -{ - return is_write && size == 4; -} - -static const MemoryRegionOps sys_ops = { - .write = sys_write, - .valid.accepts = sys_ops_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, -}; - -static void sys_reset(DeviceState *d) -{ - LM32SysState *s = LM32_SYS(d); - int i; - - for (i = 0; i < R_MAX; i++) { - s->regs[i] = 0; - } - memset(s->testname, 0, MAX_TESTNAME_LEN); -} - -static int lm32_sys_init(SysBusDevice *dev) -{ - LM32SysState *s = LM32_SYS(dev); - - memory_region_init_io(&s->iomem, OBJECT(dev), &sys_ops , s, - "sys", R_MAX * 4); - sysbus_init_mmio(dev, &s->iomem); - - /* Note: This device is not created in the board initialization, - * instead it has to be added with the -device parameter. Therefore, - * the device maps itself. */ - sysbus_mmio_map(dev, 0, s->base); - - return 0; -} - -static const VMStateDescription vmstate_lm32_sys = { - .name = "lm32-sys", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX), - VMSTATE_BUFFER(testname, LM32SysState), - VMSTATE_END_OF_LIST() - } -}; - -static Property lm32_sys_properties[] = { - DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000), - DEFINE_PROP_END_OF_LIST(), -}; - -static void lm32_sys_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); - - k->init = lm32_sys_init; - dc->reset = sys_reset; - dc->vmsd = &vmstate_lm32_sys; - dc->props = lm32_sys_properties; -} - -static const TypeInfo lm32_sys_info = { - .name = TYPE_LM32_SYS, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LM32SysState), - .class_init = lm32_sys_class_init, -}; - -static void lm32_sys_register_types(void) -{ - type_register_static(&lm32_sys_info); -} - -type_init(lm32_sys_register_types) diff --git a/target-lm32/README b/target-lm32/README index 03ddbff..ba3508a 100644 --- a/target-lm32/README +++ b/target-lm32/README @@ -16,16 +16,6 @@ This will make serial0 (the lm32_uart) and serial1 (the JTAG UART) available as virtual consoles. -Programmatically terminate the emulator ----------------------------------------- -Originally neither the LatticeMico32 nor its peripherals support a -mechanism to shut down the machine. Emulation aware programs can write to a -to a special register within the system control block to shut down the -virtual machine. For more details see hw/lm32_sys.c. The lm32-evr is the -first BSP which instantiate this model. A (32 bit) write to 0xfff0000 -causes a vm shutdown. - - Semihosting ----------- Semihosting on this target is supported. Some system calls like read, write diff --git a/trace-events b/trace-events index b6d289d..7a415d9 100644 --- a/trace-events +++ b/trace-events @@ -627,9 +627,6 @@ lm32_uart_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" lm32_uart_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" lm32_uart_irq_state(int level) "irq state %d" -# hw/misc/lm32_sys.c -lm32_sys_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" - # hw/scsi/megasas.c megasas_init_firmware(uint64_t pa) "pa %" PRIx64 " " megasas_init_queue(uint64_t queue_pa, int queue_len, uint64_t head, uint64_t tail, uint32_t flags) "queue at %" PRIx64 " len %d head %" PRIx64 " tail %" PRIx64 " flags %x"