From patchwork Sat May 24 15:53:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 352137 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BCD4C140081 for ; Sun, 25 May 2014 02:06:51 +1000 (EST) Received: from localhost ([::1]:48591 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoETA-0003gG-QM for incoming@patchwork.ozlabs.org; Sat, 24 May 2014 12:06:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoEHR-0003Oo-EQ for qemu-devel@nongnu.org; Sat, 24 May 2014 11:54:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WoEHL-0001JC-AS for qemu-devel@nongnu.org; Sat, 24 May 2014 11:54:41 -0400 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]:63239) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WoEHK-0001Iz-QX for qemu-devel@nongnu.org; Sat, 24 May 2014 11:54:35 -0400 Received: by mail-pa0-f45.google.com with SMTP id ey11so5491963pad.18 for ; Sat, 24 May 2014 08:54:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=PJq6l+H7YHt8ctKYtg0ikL35z6GuFjlgaV5LdD5tykY=; b=aTQlO7m694Qgxz7xxSHmh6WsTYV4d3uI/P6D1Jo/4QAUPmbG75Pzk2AWdFm9qXfrzU Nk468a787q2liNfoBdWD99Or+4P4d5RuB2jVnz6Mcb0CLqS5oR4ZtV4grBYAvU9Q/UPX 58+QZ5QREpUzpvIrItN76TfpT+ZGGJYRDFNPbD4afMjZ86efwrVA7ITtRZybSGbxcLiQ jjAGKVEpzRfIHih94BQ9JCJ2F/vS3m4N2hUPmQR49UzvuQkidsECHFF9fYSn3yiyTV50 e8dOXoGfL2bFtSRWaxVQ18zcTlAbInXqrWkym38qlHUDHn8zc0DB7/ydUb60HisVRNY6 x8BA== X-Received: by 10.66.240.130 with SMTP id wa2mr14668020pac.73.1400946873433; Sat, 24 May 2014 08:54:33 -0700 (PDT) Received: from pike.twiddle.home (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id ie9sm30663048pad.29.2014.05.24.08.54.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 May 2014 08:54:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 24 May 2014 08:53:52 -0700 Message-Id: <1400946841-21079-16-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1400946841-21079-1-git-send-email-rth@twiddle.net> References: <1400946841-21079-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22d Cc: peter.maydell@linaro.org Subject: [Qemu-devel] [PULL 15/24] tcg-mips: Hoist args loads X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 201 ++++++++++++++++++++++++++------------------------ 1 file changed, 103 insertions(+), 98 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 5021dea..516c2b7 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1345,10 +1345,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - switch(opc) { + TCGArg a0, a1, a2; + int c2; + + a0 = args[0]; + a1 = args[1]; + a2 = args[2]; + c2 = const_args[2]; + + switch (opc) { case INDEX_op_exit_tb: { - uintptr_t a0 = args[0]; TCGReg b0 = TCG_REG_ZERO; if (a0 & ~0xffff) { @@ -1370,237 +1377,235 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } else { /* indirect jump method */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_next + args[0])); + (uintptr_t)(s->tb_next + a0)); tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); } tcg_out_nop(s); - s->tb_next_offset[args[0]] = tcg_current_code_size(s); + s->tb_next_offset[a0] = tcg_current_code_size(s); break; case INDEX_op_br: - tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, args[0]); + tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, a0); break; case INDEX_op_ld8u_i32: - tcg_out_ldst(s, OPC_LBU, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_LBU, a0, a1, a2); break; case INDEX_op_ld8s_i32: - tcg_out_ldst(s, OPC_LB, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_LB, a0, a1, a2); break; case INDEX_op_ld16u_i32: - tcg_out_ldst(s, OPC_LHU, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_LHU, a0, a1, a2); break; case INDEX_op_ld16s_i32: - tcg_out_ldst(s, OPC_LH, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_LH, a0, a1, a2); break; case INDEX_op_ld_i32: - tcg_out_ldst(s, OPC_LW, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_LW, a0, a1, a2); break; case INDEX_op_st8_i32: - tcg_out_ldst(s, OPC_SB, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_SB, a0, a1, a2); break; case INDEX_op_st16_i32: - tcg_out_ldst(s, OPC_SH, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_SH, a0, a1, a2); break; case INDEX_op_st_i32: - tcg_out_ldst(s, OPC_SW, args[0], args[1], args[2]); + tcg_out_ldst(s, OPC_SW, a0, a1, a2); break; case INDEX_op_add_i32: - if (const_args[2]) { - tcg_out_opc_imm(s, OPC_ADDIU, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_imm(s, OPC_ADDIU, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_ADDU, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_ADDU, a0, a1, a2); } break; case INDEX_op_add2_i32: if (const_args[4]) { - tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP0, args[2], args[4]); + tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP0, a2, args[4]); } else { - tcg_out_opc_reg(s, OPC_ADDU, TCG_TMP0, args[2], args[4]); + tcg_out_opc_reg(s, OPC_ADDU, TCG_TMP0, a2, args[4]); } - tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP1, TCG_TMP0, args[2]); + tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP1, TCG_TMP0, a2); if (const_args[5]) { - tcg_out_opc_imm(s, OPC_ADDIU, args[1], args[3], args[5]); + tcg_out_opc_imm(s, OPC_ADDIU, a1, args[3], args[5]); } else { - tcg_out_opc_reg(s, OPC_ADDU, args[1], args[3], args[5]); + tcg_out_opc_reg(s, OPC_ADDU, a1, args[3], args[5]); } - tcg_out_opc_reg(s, OPC_ADDU, args[1], args[1], TCG_TMP1); - tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_TMP0); + tcg_out_opc_reg(s, OPC_ADDU, a1, a1, TCG_TMP1); + tcg_out_mov(s, TCG_TYPE_I32, a0, TCG_TMP0); break; case INDEX_op_sub_i32: - if (const_args[2]) { - tcg_out_opc_imm(s, OPC_ADDIU, args[0], args[1], -args[2]); + if (c2) { + tcg_out_opc_imm(s, OPC_ADDIU, a0, a1, -a2); } else { - tcg_out_opc_reg(s, OPC_SUBU, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_SUBU, a0, a1, a2); } break; case INDEX_op_sub2_i32: if (const_args[4]) { - tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP0, args[2], -args[4]); + tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP0, a2, -args[4]); } else { - tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, args[2], args[4]); + tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, a2, args[4]); } - tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP1, args[2], TCG_TMP0); + tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP1, a2, TCG_TMP0); if (const_args[5]) { - tcg_out_opc_imm(s, OPC_ADDIU, args[1], args[3], -args[5]); + tcg_out_opc_imm(s, OPC_ADDIU, a1, args[3], -args[5]); } else { - tcg_out_opc_reg(s, OPC_SUBU, args[1], args[3], args[5]); + tcg_out_opc_reg(s, OPC_SUBU, a1, args[3], args[5]); } - tcg_out_opc_reg(s, OPC_SUBU, args[1], args[1], TCG_TMP1); - tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_TMP0); + tcg_out_opc_reg(s, OPC_SUBU, a1, a1, TCG_TMP1); + tcg_out_mov(s, TCG_TYPE_I32, a0, TCG_TMP0); break; case INDEX_op_mul_i32: if (use_mips32_instructions) { - tcg_out_opc_reg(s, OPC_MUL, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_MULT, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); } break; case INDEX_op_muls2_i32: - tcg_out_opc_reg(s, OPC_MULT, 0, args[2], args[3]); - tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); - tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0); + tcg_out_opc_reg(s, OPC_MULT, 0, a2, args[3]); + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); + tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); break; case INDEX_op_mulu2_i32: - tcg_out_opc_reg(s, OPC_MULTU, 0, args[2], args[3]); - tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); - tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0); + tcg_out_opc_reg(s, OPC_MULTU, 0, a2, args[3]); + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); + tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); break; case INDEX_op_mulsh_i32: - tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_MULT, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); break; case INDEX_op_muluh_i32: - tcg_out_opc_reg(s, OPC_MULTU, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_MULTU, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); break; case INDEX_op_div_i32: - tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_DIV, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); break; case INDEX_op_divu_i32: - tcg_out_opc_reg(s, OPC_DIVU, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_DIVU, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); break; case INDEX_op_rem_i32: - tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_DIV, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); break; case INDEX_op_remu_i32: - tcg_out_opc_reg(s, OPC_DIVU, 0, args[1], args[2]); - tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_DIVU, 0, a1, a2); + tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); break; case INDEX_op_and_i32: - if (const_args[2]) { - if (args[2] == (uint16_t)args[2]) { - tcg_out_opc_imm(s, OPC_ANDI, args[0], args[1], args[2]); + if (c2) { + if (a2 == (uint16_t)a2) { + tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); } else { - int msb = ctz32(~args[2]) - 1; + int msb = ctz32(~a2) - 1; assert(use_mips32r2_instructions); - assert(is_p2m1(args[2])); - tcg_out_opc_bf(s, OPC_EXT, args[0], args[1], msb, 0); + assert(is_p2m1(a2)); + tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); } } else { - tcg_out_opc_reg(s, OPC_AND, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); } break; case INDEX_op_or_i32: - if (const_args[2]) { - tcg_out_opc_imm(s, OPC_ORI, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_OR, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); } break; case INDEX_op_nor_i32: - tcg_out_opc_reg(s, OPC_NOR, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); break; case INDEX_op_not_i32: - tcg_out_opc_reg(s, OPC_NOR, args[0], TCG_REG_ZERO, args[1]); + tcg_out_opc_reg(s, OPC_NOR, a0, TCG_REG_ZERO, a1); break; case INDEX_op_xor_i32: - if (const_args[2]) { - tcg_out_opc_imm(s, OPC_XORI, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_XOR, args[0], args[1], args[2]); + tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); } break; case INDEX_op_sar_i32: - if (const_args[2]) { - tcg_out_opc_sa(s, OPC_SRA, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_SRAV, args[0], args[2], args[1]); + tcg_out_opc_reg(s, OPC_SRAV, a0, a2, a1); } break; case INDEX_op_shl_i32: - if (const_args[2]) { - tcg_out_opc_sa(s, OPC_SLL, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_SLLV, args[0], args[2], args[1]); + tcg_out_opc_reg(s, OPC_SLLV, a0, a2, a1); } break; case INDEX_op_shr_i32: - if (const_args[2]) { - tcg_out_opc_sa(s, OPC_SRL, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_SRLV, args[0], args[2], args[1]); + tcg_out_opc_reg(s, OPC_SRLV, a0, a2, a1); } break; case INDEX_op_rotl_i32: - if (const_args[2]) { - tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], 0x20 - args[2]); + if (c2) { + tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); } else { - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP0, 32); - tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_TMP0, args[2]); - tcg_out_opc_reg(s, OPC_ROTRV, args[0], TCG_TMP0, args[1]); + tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); + tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); } break; case INDEX_op_rotr_i32: - if (const_args[2]) { - tcg_out_opc_sa(s, OPC_ROTR, args[0], args[1], args[2]); + if (c2) { + tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); } else { - tcg_out_opc_reg(s, OPC_ROTRV, args[0], args[2], args[1]); + tcg_out_opc_reg(s, OPC_ROTRV, a0, a2, a1); } break; case INDEX_op_bswap16_i32: - tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]); + tcg_out_opc_reg(s, OPC_WSBH, a0, 0, a1); break; case INDEX_op_bswap32_i32: - tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]); - tcg_out_opc_sa(s, OPC_ROTR, args[0], args[0], 16); + tcg_out_opc_reg(s, OPC_WSBH, a0, 0, a1); + tcg_out_opc_sa(s, OPC_ROTR, a0, a0, 16); break; case INDEX_op_ext8s_i32: - tcg_out_opc_reg(s, OPC_SEB, args[0], 0, args[1]); + tcg_out_opc_reg(s, OPC_SEB, a0, 0, a1); break; case INDEX_op_ext16s_i32: - tcg_out_opc_reg(s, OPC_SEH, args[0], 0, args[1]); + tcg_out_opc_reg(s, OPC_SEH, a0, 0, a1); break; case INDEX_op_deposit_i32: - tcg_out_opc_bf(s, OPC_INS, args[0], args[2], - args[3] + args[4] - 1, args[3]); + tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); break; case INDEX_op_brcond_i32: - tcg_out_brcond(s, args[2], args[0], args[1], args[3]); + tcg_out_brcond(s, a2, a0, a1, args[3]); break; case INDEX_op_brcond2_i32: - tcg_out_brcond2(s, args[4], args[0], args[1], args[2], args[3], args[5]); + tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], args[5]); break; case INDEX_op_movcond_i32: - tcg_out_movcond(s, args[5], args[0], args[1], args[2], args[3]); + tcg_out_movcond(s, args[5], a0, a1, a2, args[3]); break; case INDEX_op_setcond_i32: - tcg_out_setcond(s, args[3], args[0], args[1], args[2]); + tcg_out_setcond(s, args[3], a0, a1, a2); break; case INDEX_op_setcond2_i32: - tcg_out_setcond2(s, args[5], args[0], args[1], args[2], args[3], args[4]); + tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); break; case INDEX_op_qemu_ld_i32: