From patchwork Fri May 23 15:20:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 351895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 14FD1140079 for ; Sat, 24 May 2014 01:27:52 +1000 (EST) Received: from localhost ([::1]:44101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnrNt-0004xB-SN for incoming@patchwork.ozlabs.org; Fri, 23 May 2014 11:27:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52130) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnrHt-0003fb-Cu for qemu-devel@nongnu.org; Fri, 23 May 2014 11:21:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WnrHn-0005RL-RH for qemu-devel@nongnu.org; Fri, 23 May 2014 11:21:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34913) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WnrHn-0005P2-Jo for qemu-devel@nongnu.org; Fri, 23 May 2014 11:21:31 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id s4NFLTww008656 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 23 May 2014 11:21:29 -0400 Received: from playground.usersys.redhat.com (ovpn-112-34.ams2.redhat.com [10.36.112.34]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id s4NFKw2B020365; Fri, 23 May 2014 11:21:27 -0400 From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Fri, 23 May 2014 17:20:55 +0200 Message-Id: <1400858457-20391-12-git-send-email-pbonzini@redhat.com> In-Reply-To: <1400858457-20391-1-git-send-email-pbonzini@redhat.com> References: <1400858457-20391-1-git-send-email-pbonzini@redhat.com> X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: peter.maydell@linaro.org, afaerber@suse.de Subject: [Qemu-devel] [PATCH 11/13] target-arm: move arm_*_code to a separate file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These will soon require cpu_ldst.h, so move them out of cpu.h. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target-arm/arm_ldst.h | 47 ++++++++++++++++++++++++++++++++++++++++++++ target-arm/cpu.h | 22 -------------------- target-arm/helper.c | 1 + target-arm/translate-a64.c | 1 + target-arm/translate.c | 1 + 5 files changed, 50 insertions(+), 22 deletions(-) create mode 100644 target-arm/arm_ldst.h diff --git a/target-arm/arm_ldst.h b/target-arm/arm_ldst.h new file mode 100644 index 0000000..007a7d7 --- /dev/null +++ b/target-arm/arm_ldst.h @@ -0,0 +1,47 @@ +/* + * ARM load/store instructions for code (armeb-user support) + * + * Copyright (c) 2012 CodeSourcery, LLC + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef ARM_LDST_H +#define ARM_LDST_H + +#include "qemu/bswap.h" + +/* Load an instruction and return it in the standard little-endian order */ +static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, + bool do_swap) +{ + uint32_t insn = cpu_ldl_code(env, addr); + if (do_swap) { + return bswap32(insn); + } + return insn; +} + +/* Ditto, for a halfword (Thumb) instruction */ +static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, + bool do_swap) +{ + uint16_t insn = cpu_lduw_code(env, addr); + if (do_swap) { + return bswap16(insn); + } + return insn; +} + +#endif diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c83f249..b4ee31b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1195,26 +1195,4 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) } } -/* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, - bool do_swap) -{ - uint32_t insn = cpu_ldl_code(env, addr); - if (do_swap) { - return bswap32(insn); - } - return insn; -} - -/* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, - bool do_swap) -{ - uint16_t insn = cpu_lduw_code(env, addr); - if (do_swap) { - return bswap16(insn); - } - return insn; -} - #endif diff --git a/target-arm/helper.c b/target-arm/helper.c index 417161e..4a54c9e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7,6 +7,7 @@ #include "sysemu/sysemu.h" #include "qemu/bitops.h" #include "qemu/crc32c.h" +#include "arm_ldst.h" #include /* For crc32 */ #ifndef CONFIG_USER_ONLY diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index b62db4d..fc09a36 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "tcg-op.h" #include "qemu/log.h" +#include "arm_ldst.h" #include "translate.h" #include "internals.h" #include "qemu/host-utils.h" diff --git a/target-arm/translate.c b/target-arm/translate.c index a4d920b..6916f9f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -30,6 +30,7 @@ #include "tcg-op.h" #include "qemu/log.h" #include "qemu/bitops.h" +#include "arm_ldst.h" #include "helper.h" #define GEN_HELPER 1