From patchwork Fri May 16 18:13:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 349708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0F2D3140098 for ; Sat, 17 May 2014 04:15:55 +1000 (EST) Received: from localhost ([::1]:37213 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WlMfg-0003iR-Tg for incoming@patchwork.ozlabs.org; Fri, 16 May 2014 14:15:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WlMf0-0002uf-OH for qemu-devel@nongnu.org; Fri, 16 May 2014 14:15:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WlMet-0007h2-Mp for qemu-devel@nongnu.org; Fri, 16 May 2014 14:15:10 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:46870 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WlMet-0007aS-D3 for qemu-devel@nongnu.org; Fri, 16 May 2014 14:15:03 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6ED231A1DB4; Fri, 16 May 2014 20:14:37 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from mail.rt-rk.com ([127.0.0.1]) by localhost (mail.rt-rk.com [127.0.0.1]) (amavisd-new, port 10026) with LMTP id ZkmgQHmHRh2A; Fri, 16 May 2014 20:14:37 +0200 (CEST) Received: from mcs14.domain.local (mcs14.domain.local [192.168.236.230]) by mail.rt-rk.com (Postfix) with ESMTPSA id 547DC1A1D9E; Fri, 16 May 2014 20:14:37 +0200 (CEST) From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Fri, 16 May 2014 20:13:34 +0200 Message-Id: <1400264014-78911-3-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1400264014-78911-1-git-send-email-petar.jovanovic@rt-rk.com> References: <1400264014-78911-1-git-send-email-petar.jovanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 2/2] target-mips: implement UserLocal Register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic From MIPS documentation (Volume III): UserLocal Register (CP0 Register 4, Select 2) Compliance Level: Recommended. The UserLocal register is a read-write register that is not interpreted by the hardware and conditionally readable via the RDHWR instruction. This register only exists if the Config3-ULRI register field is set. Privileged software may write this register with arbitrary information and make it accessable to unprivileged software via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register. Signed-off-by: Petar Jovanovic --- target-mips/cpu.h | 2 ++ target-mips/helper.h | 1 + target-mips/op_helper.c | 20 +++++++++++++++++++- target-mips/translate.c | 43 +++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 63 insertions(+), 3 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6c2014e..bb18fb8 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -227,6 +227,7 @@ struct CPUMIPSState { target_ulong CP0_EntryLo0; target_ulong CP0_EntryLo1; target_ulong CP0_Context; + target_ulong CP0_UserLocal; int32_t CP0_PageMask; int32_t CP0_PageGrain; int32_t CP0_Wired; @@ -361,6 +362,7 @@ struct CPUMIPSState { int32_t CP0_Config3; #define CP0C3_M 31 #define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ULRI 13 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 diff --git a/target-mips/helper.h b/target-mips/helper.h index 8c7921a..ec56199 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -296,6 +296,7 @@ DEF_HELPER_1(rdhwr_cpunum, tl, env) DEF_HELPER_1(rdhwr_synci_step, tl, env) DEF_HELPER_1(rdhwr_cc, tl, env) DEF_HELPER_1(rdhwr_ccres, tl, env) +DEF_HELPER_1(rdhwr_ul, tl, env) DEF_HELPER_2(pmon, void, env, int) DEF_HELPER_1(wait, void, env) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 4edec6c..72c0a25 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1301,7 +1301,13 @@ void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) { - env->CP0_HWREna = arg1 & 0x0000000F; + uint32_t mask = 0x0000000F; + + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { + mask |= 0x20000000; + } + + env->CP0_HWREna = arg1 & mask; } void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) @@ -2091,6 +2097,18 @@ target_ulong helper_rdhwr_ccres(CPUMIPSState *env) return 0; } +target_ulong helper_rdhwr_ul(CPUMIPSState *env) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || + (env->CP0_HWREna & (1 << 29))) { + return env->CP0_UserLocal; + } else { + helper_raise_exception(env, EXCP_RI); + } + + return 0; +} + void helper_pmon(CPUMIPSState *env, int function) { function /= 2; diff --git a/target-mips/translate.c b/target-mips/translate.c index d629b73..792da07 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4216,7 +4216,17 @@ static void gen_mfc0(CPUMIPSState *env, DisasContext *ctx, case 1: // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */ rn = "ContextConfig"; + goto die; // break; + case 2: + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_UserLocal)); + tcg_gen_ext32s_tl(arg, arg); + rn = "UserLocal"; + } else { + tcg_gen_movi_tl(arg, 0); + } default: goto die; } @@ -4804,7 +4814,15 @@ static void gen_mtc0(CPUMIPSState *env, DisasContext *ctx, case 1: // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; + goto die; // break; + case 2: + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_UserLocal)); + rn = "UserLocal"; + } + break; default: goto die; } @@ -5409,7 +5427,17 @@ static void gen_dmfc0(CPUMIPSState *env, DisasContext *ctx, case 1: // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */ rn = "ContextConfig"; + goto die; // break; + case 2: + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { + tcg_gen_ld_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_UserLocal)); + rn = "UserLocal"; + } else { + tcg_gen_movi_tl(arg, 0); + } + break; default: goto die; } @@ -5982,7 +6010,15 @@ static void gen_dmtc0(CPUMIPSState *env, DisasContext *ctx, case 1: // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */ rn = "ContextConfig"; + goto die; // break; + case 2: + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_UserLocal)); + rn = "UserLocal"; + } + break; default: goto die; } @@ -9068,8 +9104,10 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd) gen_store_gpr(t0, rt); break; #else - /* XXX: Some CPUs implement this in hardware. - Not supported yet. */ + save_cpu_state(ctx, 1); + gen_helper_rdhwr_ul(t0, cpu_env); + gen_store_gpr(t0, rt); + break; #endif default: /* Invalid */ MIPS_INVAL("rdhwr"); @@ -16034,6 +16072,7 @@ void cpu_state_reset(CPUMIPSState *env) /* vectored interrupts not implemented, timer on int 7, no performance counters. */ env->CP0_IntCtl = 0xe0000000; + env->CP0_UserLocal = 0; { int i;