Message ID | 1396450172-31322-1-git-send-email-chouteau@adacore.com |
---|---|
State | New |
Headers | show |
On 02.04.2014, at 16:49, Fabien Chouteau <chouteau@adacore.com> wrote: > IRQ are lowered when ievent bit is cleared, so irq_pulse makes no sense > here... > > Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Thanks, applied to ppc-next. Given that the wiring with boards is still missing I don't think this is a critical 2.0 fix. Alex
On 04/02/2014 04:52 PM, Alexander Graf wrote: > > On 02.04.2014, at 16:49, Fabien Chouteau <chouteau@adacore.com> wrote: > >> IRQ are lowered when ievent bit is cleared, so irq_pulse makes no sense >> here... >> >> Signed-off-by: Fabien Chouteau <chouteau@adacore.com> > > Thanks, applied to ppc-next. Thanks Alex, > Given that the wiring with boards is still missing I don't think this is a critical 2.0 fix. > That's right. Regards,
diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c index e36cfbe..d4a494f 100644 --- a/hw/net/fsl_etsec/rings.c +++ b/hw/net/fsl_etsec/rings.c @@ -159,7 +159,7 @@ static void ievent_set(eTSEC *etsec, if ((flags & IEVENT_RXB && etsec->regs[IMASK].value & IMASK_RXBEN) || (flags & IEVENT_RXF && etsec->regs[IMASK].value & IMASK_RXFEN)) { - qemu_irq_pulse(etsec->rx_irq); + qemu_irq_raise(etsec->rx_irq); RING_DEBUG("%s Raise Rx IRQ\n", __func__); } }
IRQ are lowered when ievent bit is cleared, so irq_pulse makes no sense here... Signed-off-by: Fabien Chouteau <chouteau@adacore.com> --- hw/net/fsl_etsec/rings.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)