From patchwork Sun Feb 2 23:17:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 316040 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CCAD02C007A for ; Mon, 3 Feb 2014 10:19:30 +1100 (EST) Received: from localhost ([::1]:43101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WA6Jz-0000oR-R8 for incoming@patchwork.ozlabs.org; Sun, 02 Feb 2014 18:19:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WA6II-0007qm-Dl for qemu-devel@nongnu.org; Sun, 02 Feb 2014 18:17:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WA6IC-0007gr-Fy for qemu-devel@nongnu.org; Sun, 02 Feb 2014 18:17:42 -0500 Received: from mail-pd0-f170.google.com ([209.85.192.170]:62340) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WA6IC-0007gf-7L for qemu-devel@nongnu.org; Sun, 02 Feb 2014 18:17:36 -0500 Received: by mail-pd0-f170.google.com with SMTP id p10so6217016pdj.15 for ; Sun, 02 Feb 2014 15:17:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CFCUOxGvdRB6x61OuyKeE5DjcVBc9VUTQsxBvj9zErE=; b=lgC1m4axi7P3Fo2lhykzrowyQW7oyxMgBXqoWCEFesq91rV/y7+iB/PbAJzrv9NOY0 Hk+XcY3A6XyYAQtWdUx5la16X10jXYWmDuQOqbEqbQOmDp57xk3x9o6iPzKXj3MgS1xA OB0iAy58A6DQBSRt8rG8PhDlcPqBIjOujf8ME8hGn7N+8s9sEKsaTAn0Mm0ztWl6PNw9 bksrfSd/dns0g6xhCyaavq4XB0xlYY6mMZKe2dYBO/c+glKLulH2P/sSPU3/kffbJosu xuDsiYHZOckpkV0NPLOYnP+pkAcBW9aU/fo63so1KbmUAHpZs8SZSVxyGAYybrpIfQsE h7pw== X-Gm-Message-State: ALoCoQlXpfAXnRDyxacJdTlOoTi9r0uomPN9b7L7CGA00vUK9SDF2ciZwfEdB3In7hlRXtDyiKIA X-Received: by 10.66.194.2 with SMTP id hs2mr33545181pac.79.1391383055608; Sun, 02 Feb 2014 15:17:35 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id qq5sm49777615pbb.24.2014.02.02.15.17.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 02 Feb 2014 15:17:34 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Sun, 2 Feb 2014 15:17:23 -0800 Message-Id: <1391383044-596-6-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.5.2 In-Reply-To: <1391383044-596-1-git-send-email-christoffer.dall@linaro.org> References: <1391383044-596-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.170 Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Subject: [Qemu-devel] [PATCH v6 5/6] arm_gic: Add GICC_APRn state to the GICState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: Peter Maydell Signed-off-by: Christoffer Dall --- Changes [v4 -> v5]: - Add TODO comment about reworking last_active and running_irq to use te new field instead. Changes [v3 -> v4]: - Fixed grammatical error and use qemu_log_mask for print. hw/intc/arm_gic.c | 5 +++++ hw/intc/arm_gic_common.c | 5 +++-- include/hw/intc/arm_gic_common.h | 19 +++++++++++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5413a24..93eaa6b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -678,6 +678,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ return s->abpr[cpu]; + case 0xd0: case 0xd4: case 0xd8: case 0xdc: + return s->apr[(offset - 0xd0) / 4][cpu]; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); @@ -705,6 +707,9 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->abpr[cpu] = (value & 0x7); } break; + case 0xd0: case 0xd4: case 0xd8: case 0xdc: + qemu_log_mask(LOG_UNIMP, "Writing APR not implemented\n"); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index d2d8ce1..6d884ec 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = { static const VMStateDescription vmstate_gic = { .name = "arm_gic", - .version_id = 6, - .minimum_version_id = 6, + .version_id = 7, + .minimum_version_id = 7, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { @@ -78,6 +78,7 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), + VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 0f0644b..f6887ed 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -31,6 +31,9 @@ /* Maximum number of possible CPU interfaces, determined by GIC architecture */ #define GIC_NCPU 8 +#define MAX_NR_GROUP_PRIO 128 +#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) + typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ uint8_t enabled; @@ -75,6 +78,22 @@ typedef struct GICState { uint8_t bpr[GIC_NCPU]; uint8_t abpr[GIC_NCPU]; + /* The APR is implementation defined, so we choose a layout identical to + * the KVM ABI layout for QEMU's implementation of the gic: + * If an interrupt for preemption level X is active, then + * APRn[X mod 32] == 0b1, where n = X / 32 + * otherwise the bit is clear. + * + * TODO: rewrite the interrupt acknowlege/complete routines to use + * the APR registers to track the necessary information to update + * s->running_priority[] on interrupt completion (ie completely remove + * last_active[][] and running_irq[]). This will be necessary if we ever + * want to support TCG<->KVM migration, or TCG guests which can + * do power management involving powering down and restarting + * the GIC. + */ + uint32_t apr[GIC_NR_APRS][GIC_NCPU]; + uint32_t num_cpu; MemoryRegion iomem; /* Distributor */