| Message ID | 1391183143-30724-24-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 31 January 2014 15:45, Peter Maydell <peter.maydell@linaro.org> wrote: > Implement all the AArch64 cache invalidate and clean ops > (which are all NOPs since QEMU doesn't emulate the cache). > The only remaining unimplemented cache op is DC ZVA. Alex pointed out to me on IRC that since userspace can use these operations we really need them for linux-user mode. I'd appreciate review on the various bits of this patchset that are dependencies for getting this into master before 2.0 freeze (whenever that is)... thanks -- PMM
On Sat, Feb 1, 2014 at 1:45 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > Implement all the AArch64 cache invalidate and clean ops > (which are all NOPs since QEMU doesn't emulate the cache). > The only remaining unimplemented cache op is DC ZVA. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> > --- > target-arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 82efbfa..b9ed707 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -1533,6 +1533,18 @@ static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, > env->pstate |= (value & PSTATE_DAIF); > } > > +static CPAccessResult aa64_cacheop_access(CPUARMState *env, > + const ARMCPRegInfo *ri) > +{ > + /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless > + * SCTLR_EL1.UCI is set. > + */ > + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) { > + return CP_ACCESS_TRAP; > + } > + return CP_ACCESS_OK; > +} > + > static const ARMCPRegInfo v8_cp_reginfo[] = { > /* Minimal set of EL0-visible registers. This will need to be expanded > * significantly for system emulation of AArch64 CPUs. > @@ -1561,6 +1573,41 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, > .access = PL1_R, .type = ARM_CP_CURRENTEL }, > + /* Cache ops: all NOPs since we don't emulate caches */ > + { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, > + .access = PL1_W, .type = ARM_CP_NOP }, > + { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, > + .access = PL0_W, .type = ARM_CP_NOP, > + .accessfn = aa64_cacheop_access }, > + { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, > + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, > + .access = PL1_W, .type = ARM_CP_NOP }, > REGINFO_SENTINEL > }; > > -- > 1.8.5 > >
diff --git a/target-arm/helper.c b/target-arm/helper.c index 82efbfa..b9ed707 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1533,6 +1533,18 @@ static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, env->pstate |= (value & PSTATE_DAIF); } +static CPAccessResult aa64_cacheop_access(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless + * SCTLR_EL1.UCI is set. + */ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v8_cp_reginfo[] = { /* Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. @@ -1561,6 +1573,41 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, .access = PL1_R, .type = ARM_CP_CURRENTEL }, + /* Cache ops: all NOPs since we don't emulate caches */ + { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NOP, + .accessfn = aa64_cacheop_access }, + { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NOP, + .accessfn = aa64_cacheop_access }, + { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NOP, + .accessfn = aa64_cacheop_access }, + { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1, + .access = PL0_W, .type = ARM_CP_NOP, + .accessfn = aa64_cacheop_access }, + { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, + .access = PL1_W, .type = ARM_CP_NOP }, REGINFO_SENTINEL };
Implement all the AArch64 cache invalidate and clean ops (which are all NOPs since QEMU doesn't emulate the cache). The only remaining unimplemented cache op is DC ZVA. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+)