From patchwork Fri Jan 24 16:18:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 313937 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 08EF12C008F for ; Sat, 25 Jan 2014 03:31:18 +1100 (EST) Received: from localhost ([::1]:47557 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W6jf1-0007js-Tp for incoming@patchwork.ozlabs.org; Fri, 24 Jan 2014 11:31:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W6jUP-00009R-IO for qemu-devel@nongnu.org; Fri, 24 Jan 2014 11:20:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W6jUE-0004B5-6R for qemu-devel@nongnu.org; Fri, 24 Jan 2014 11:20:17 -0500 Received: from mail.rt-rk.ftn.uns.ac.rs ([147.91.177.140]:39131 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W6jUD-000495-TB for qemu-devel@nongnu.org; Fri, 24 Jan 2014 11:20:06 -0500 Received: from mail.rt-rk.com (mail.localdomain [127.0.0.1]) by mail.rt-rk.com (Postfix) with SMTP id 6C71725B989 for ; Fri, 24 Jan 2014 17:20:05 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Fri, 24 Jan 2014 17:18:41 +0100 Message-Id: <1390580324-1924-2-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1390580324-1924-1-git-send-email-petar.jovanovic@rt-rk.com> References: <1390580324-1924-1-git-send-email-petar.jovanovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.91.177.140 Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic Add mips32r5-generic among CPU definitions for MIPS. Define ISA_MIPS32R3 and ISA_MIPS32R5. Signed-off-by: Petar Jovanovic --- target-mips/mips-defs.h | 8 ++++++++ target-mips/translate_init.c | 25 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index bf094a3..9dfa516 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -29,6 +29,8 @@ #define ISA_MIPS32R2 0x00000040 #define ISA_MIPS64 0x00000080 #define ISA_MIPS64R2 0x00000100 +#define ISA_MIPS32R3 0x00000200 +#define ISA_MIPS32R5 0x00000400 /* MIPS ASEs. */ #define ASE_MIPS16 0x00001000 @@ -64,6 +66,12 @@ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) +/* MIPS Technologies "Release 3" */ +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) + +/* MIPS Technologies "Release 5" */ +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c45b1b2..d74a0af 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, .mmu_type = MMU_TYPE_R4000, }, + { + /* A generic CPU providing MIPS32 Release 5 features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "mips32r5-generic", + .CP0_PRid = 0x00019700, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name = "R4000",