From patchwork Tue Jan 7 21:00:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 307883 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 50D982C00CB for ; Wed, 8 Jan 2014 10:07:37 +1100 (EST) Received: from localhost ([::1]:42967 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dw4-00031P-2y for incoming@patchwork.ozlabs.org; Tue, 07 Jan 2014 16:11:40 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dml-0003oa-1a for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:02:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1W0dmg-0003dt-BI for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:02:02 -0500 Received: from mail-qc0-x229.google.com ([2607:f8b0:400d:c01::229]:48940) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1W0dmg-0003di-26 for qemu-devel@nongnu.org; Tue, 07 Jan 2014 16:01:58 -0500 Received: by mail-qc0-f169.google.com with SMTP id r5so697405qcx.14 for ; Tue, 07 Jan 2014 13:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KQ/QWmAXQmEBcCnvj7muT7HtkKtdjuNzYnUSp2quHAE=; b=t/H1x2QeNsZ40Wmh9G37M/EIMrJZk9AYYKx7jwpfYbFn4HYFOum2YlzRDxhZTSIZEh +LR18ctpA/AUnYHFJTub7alr0SQ9kaLxc/aR6VBEIDAuYYSVYWYljYB8MlR+hkSuR9tx TUj0T5Plu+PBaYYLrgSsJP1q719LDjn99LGXdgH7ngkFZNXTLxZ5qs1sjR7fBHVE7Mk8 7VpmQQggJsJN/sUW+FcU48YDu5hlhi8zZUoEdF7W3sC1j9GcpjX26/2vXY/mmGiKmMOB eDNE6eEU28nbZ4KGFBVoEav8dAOV2qL9mIjF4Clsg3tk1WFZTMJus69QSkOWes/bs/7s 5PxA== X-Received: by 10.224.152.11 with SMTP id e11mr161786732qaw.32.1389128517308; Tue, 07 Jan 2014 13:01:57 -0800 (PST) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id d7sm22444571qam.5.2014.01.07.13.01.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Jan 2014 13:01:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 7 Jan 2014 13:00:14 -0800 Message-Id: <1389128439-10067-25-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1389128439-10067-1-git-send-email-rth@twiddle.net> References: <1389128439-10067-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c01::229 Cc: aliguori@amazon.com Subject: [Qemu-devel] [PULL 24/49] target-i386: Remove gen_op_movl_T0_im* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Propagate the definition of gen_op_movl_T0_im to all users. The function gen_op_movl_T0_imu was unused. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target-i386/translate.c | 32 ++++++++++---------------------- 1 file changed, 10 insertions(+), 22 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 0671371..46eabe4 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -252,16 +252,6 @@ static void gen_update_cc_op(DisasContext *s) } } -static inline void gen_op_movl_T0_im(int32_t val) -{ - tcg_gen_movi_tl(cpu_T[0], val); -} - -static inline void gen_op_movl_T0_imu(uint32_t val) -{ - tcg_gen_movi_tl(cpu_T[0], val); -} - static inline void gen_op_movl_T1_im(int32_t val) { tcg_gen_movi_tl(cpu_T[1], val); @@ -3500,13 +3490,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } val = cpu_ldub_code(env, s->pc++); if (is_xmm) { - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1))); op1_offset = offsetof(CPUX86State,xmm_t0); } else { - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0))); tcg_gen_movi_tl(cpu_T[0], 0); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1))); @@ -5380,7 +5370,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, val = insn_get(env, s, ot); else val = (int8_t)insn_get(env, s, MO_8); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); gen_push_T0(s); break; case 0x8f: /* pop Ev */ @@ -5509,7 +5499,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_lea_modrm(env, s, modrm); } val = insn_get(env, s, ot); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); if (mod != 3) { gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } else { @@ -5685,7 +5675,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; case 0xb0 ... 0xb7: /* mov R, Ib */ val = insn_get(env, s, MO_8); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); gen_op_mov_reg_T0(MO_8, (b & 7) | REX_B(s)); break; case 0xb8 ... 0xbf: /* mov R, Iv */ @@ -5704,7 +5694,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, ot = dflag ? MO_32 : MO_16; val = insn_get(env, s, ot); reg = (b & 7) | REX_B(s); - gen_op_movl_T0_im(val); + tcg_gen_movi_tl(cpu_T[0], val); gen_op_mov_reg_T0(ot, reg); } break; @@ -6508,12 +6498,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, else ot = dflag ? MO_32 : MO_16; val = cpu_ldub_code(env, s->pc++); - gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); if (use_icount) gen_io_start(); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_movi_i32(cpu_tmp2_i32, val); gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32); gen_op_mov_reg_T1(ot, R_EAX); if (use_icount) { @@ -6528,14 +6517,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, else ot = dflag ? MO_32 : MO_16; val = cpu_ldub_code(env, s->pc++); - gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); gen_op_mov_TN_reg(ot, 1, R_EAX); if (use_icount) gen_io_start(); - tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); + tcg_gen_movi_i32(cpu_tmp2_i32, val); tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]); gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32); if (use_icount) { @@ -6687,7 +6675,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, offset = insn_get(env, s, ot); selector = insn_get(env, s, MO_16); - gen_op_movl_T0_im(selector); + tcg_gen_movi_tl(cpu_T[0], selector); gen_op_movl_T1_imu(offset); } goto do_lcall; @@ -6713,7 +6701,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, offset = insn_get(env, s, ot); selector = insn_get(env, s, MO_16); - gen_op_movl_T0_im(selector); + tcg_gen_movi_tl(cpu_T[0], selector); gen_op_movl_T1_imu(offset); } goto do_ljmp;