| Message ID | 1387203165-5553-7-git-send-email-james.hogan@imgtec.com |
|---|---|
| State | Superseded |
| Headers | show |
On Mon, Dec 16, 2013 at 02:12:41PM +0000, James Hogan wrote: > From: Sanjay Lal <sanjayl@kymasys.com> > > With larger set associative caches KVM can open the possibility of cache > aliasing between the memory that QEMU allocates with mmap and the > mapping into the guest address space. Therefore increase the target page > size to 16K when KVM is configured. > > Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> > Signed-off-by: James Hogan <james.hogan@imgtec.com> > Cc: Aurelien Jarno <aurelien@aurel32.net> > --- > Changes in v2: > - Expand commit message > --- > target-mips/mips-defs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h > index bf094a3..473ddf8 100644 > --- a/target-mips/mips-defs.h > +++ b/target-mips/mips-defs.h > @@ -5,7 +5,12 @@ > //#define USE_HOST_FLOAT_REGS > > /* Real pages are variable size... */ > +#ifdef CONFIG_KVM > +/* For KVM/MIPS the minimum page size is 16K due to cache aliasing issues */ > +#define TARGET_PAGE_BITS 14 > +#else > #define TARGET_PAGE_BITS 12 > +#endif > #define MIPS_TLB_MAX 128 > > #if defined(TARGET_MIPS64) I am not sure it is something correct. It means that the emulated CPU won't support 4K pages anymore, even when running in TCG mode without KVM. If the kernel maps a 4K page, in practice a 16K page is going to be mapped by the qemu tlb.
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index bf094a3..473ddf8 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -5,7 +5,12 @@ //#define USE_HOST_FLOAT_REGS /* Real pages are variable size... */ +#ifdef CONFIG_KVM +/* For KVM/MIPS the minimum page size is 16K due to cache aliasing issues */ +#define TARGET_PAGE_BITS 14 +#else #define TARGET_PAGE_BITS 12 +#endif #define MIPS_TLB_MAX 128 #if defined(TARGET_MIPS64)