From patchwork Wed Dec 11 19:16:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 300298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8B6DB2C009C for ; Thu, 12 Dec 2013 06:18:38 +1100 (EST) Received: from localhost ([::1]:59739 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqpIo-00087G-0B for incoming@patchwork.ozlabs.org; Wed, 11 Dec 2013 14:18:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44053) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqpI1-0007mv-Pz for qemu-devel@nongnu.org; Wed, 11 Dec 2013 14:17:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VqpHt-0008HK-Bq for qemu-devel@nongnu.org; Wed, 11 Dec 2013 14:17:45 -0500 Received: from mail-yh0-x22c.google.com ([2607:f8b0:4002:c01::22c]:37133) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VqpHt-0008HG-7K; Wed, 11 Dec 2013 14:17:37 -0500 Received: by mail-yh0-f44.google.com with SMTP id f64so5405692yha.3 for ; Wed, 11 Dec 2013 11:17:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3wHdggG8zg3p6u218OuY7ALI/WpDA7ViiLhcBEJLqbA=; b=ljiQ5yJ3TRZUlKvrcHfxaDmBYZfIPS5CwtIYVTM1OPjUYORu5vTcQo3giFjRaGRy0F hoJ90gUFHvgcfkYyYh/q4lVAE6zAf8nsSowKSU0vJ80MevKvmIvxsr+XA9KL9QtOeZY1 lp+mdwTrid+VOo70QQM8iv31VY1XdiaO2sb8p2d911nzTrtRb9Wznwy2VkOrD29DHds6 1Zea6px62xEtP4d3jmDBfBC0PREVJpZq5aemd9yzuGv0m1OqesDzXiJwmTdNP7hHE1Ys CdSrdeVyJC4czoc0GUl8kPA7j4hS2ILOllg3TIqpQmVykydVPU+nkRZEz4uCXmSovhr8 7vAA== X-Received: by 10.236.222.231 with SMTP id t97mr2660378yhp.125.1386789456936; Wed, 11 Dec 2013 11:17:36 -0800 (PST) Received: from tmusta-sc.rchland.ibm.com (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id x9sm11764420yhd.13.2013.12.11.11.17.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Dec 2013 11:17:36 -0800 (PST) From: Tom Musta To: qemu-devel@nongnu.org Date: Wed, 11 Dec 2013 13:16:27 -0600 Message-Id: <1386789398-5239-8-git-send-email-tommusta@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386789398-5239-1-git-send-email-tommusta@gmail.com> References: <1386789398-5239-1-git-send-email-tommusta@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4002:c01::22c Cc: Tom Musta , qemu-ppc@nongnu.org Subject: [Qemu-devel] [V2 PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the byte and halfword variants of the Store Conditional instructions. A common macro is introduced and the existing implementations of stwcx. and stdcx. are re-implemented using this macro. V2: Re-implemented gen_conditional_store() and STCX macro per comments from Richard. Signed-off-by: Tom Musta --- target-ppc/translate.c | 88 ++++++++++++++++++++++------------------------- 1 files changed, 41 insertions(+), 47 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c3d0ebe..27eef84 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3242,8 +3242,8 @@ LARX(lwarx, 4, ld32u); #if defined(CONFIG_USER_ONLY) -static void gen_conditional_store (DisasContext *ctx, TCGv EA, - int reg, int size) +static void gen_conditional_store(DisasContext *ctx, TCGv EA, + int reg, int size) { TCGv t0 = tcg_temp_new(); uint32_t save_exception = ctx->exception; @@ -3257,62 +3257,54 @@ static void gen_conditional_store (DisasContext *ctx, TCGv EA, gen_exception(ctx, POWERPC_EXCP_STCX); ctx->exception = save_exception; } -#endif - -/* stwcx. */ -static void gen_stwcx_(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_RES); - t0 = tcg_temp_local_new(); - gen_addr_reg_index(ctx, t0); - gen_check_align(ctx, t0, 0x03); -#if defined(CONFIG_USER_ONLY) - gen_conditional_store(ctx, t0, rS(ctx->opcode), 4); #else - { - int l1; +static void gen_conditional_store(DisasContext *ctx, TCGv EA, + int reg, int size) +{ + int l1; - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - l1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); - gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_reserve, -1); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); + l1 = gen_new_label(); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); + tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); + if (size == 8) { + gen_qemu_st64(ctx, cpu_gpr[reg], EA); + } else if (size == 4) { + gen_qemu_st32(ctx, cpu_gpr[reg], EA); + } else if (size == 2) { + gen_qemu_st16(ctx, cpu_gpr[reg], EA); + } else { + gen_qemu_st8(ctx, cpu_gpr[reg], EA); } + gen_set_label(l1); + tcg_gen_movi_tl(cpu_reserve, -1); +} #endif - tcg_temp_free(t0); + +#define STCX(name, len) \ +static void gen_##name(DisasContext *ctx) \ +{ \ + TCGv t0; \ + gen_set_access_type(ctx, ACCESS_RES); \ + t0 = tcg_temp_local_new(); \ + gen_addr_reg_index(ctx, t0); \ + if (len > 1) { \ + gen_check_align(ctx, t0, (len)-1); \ + } \ + gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \ + tcg_temp_free(t0); \ } +STCX(stbcx_, 1); +STCX(sthcx_, 2); +STCX(stwcx_, 4); + #if defined(TARGET_PPC64) /* ldarx */ LARX(ldarx, 8, ld64); /* stdcx. */ -static void gen_stdcx_(DisasContext *ctx) -{ - TCGv t0; - gen_set_access_type(ctx, ACCESS_RES); - t0 = tcg_temp_local_new(); - gen_addr_reg_index(ctx, t0); - gen_check_align(ctx, t0, 0x07); -#if defined(CONFIG_USER_ONLY) - gen_conditional_store(ctx, t0, rS(ctx->opcode), 8); -#else - { - int l1; - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - l1 = gen_new_label(); - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); - gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); - gen_set_label(l1); - tcg_gen_movi_tl(cpu_reserve, -1); - } -#endif - tcg_temp_free(t0); -} +STCX(stdcx_, 8); #endif /* defined(TARGET_PPC64) */ /* sync */ @@ -9460,6 +9452,8 @@ GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0x00000000, PPC_NONE, PPC2_ISA206), GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0x00000000, PPC_NONE, PPC2_ISA206), GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), +GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0x00000000, PPC_NONE, PPC2_ISA206), +GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0x00000000, PPC_NONE, PPC2_ISA206), GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), #if defined(TARGET_PPC64) GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),