From patchwork Wed Dec 4 11:54:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 296494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4D02E2C00A9 for ; Wed, 4 Dec 2013 22:56:06 +1100 (EST) Received: from localhost ([::1]:47771 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoB3k-0001Rc-Bc for incoming@patchwork.ozlabs.org; Wed, 04 Dec 2013 06:56:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoB32-0001Fx-HC for qemu-devel@nongnu.org; Wed, 04 Dec 2013 06:55:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VoB2v-0000ti-Hf for qemu-devel@nongnu.org; Wed, 04 Dec 2013 06:55:20 -0500 Received: from mail-wi0-f175.google.com ([209.85.212.175]:53790) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VoB2v-0000tc-Cj for qemu-devel@nongnu.org; Wed, 04 Dec 2013 06:55:13 -0500 Received: by mail-wi0-f175.google.com with SMTP id hi5so8080801wib.8 for ; Wed, 04 Dec 2013 03:55:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=83rzwqV+HRMf70a6bju/0iqLG2bmfRxgJN89ci5YdWA=; b=aw1kFsdHtQl3dViyMliWB9D+iTR2LWQvFxQ7OPlXdGDP7e/lZCoZoK+ema2495+e5q f+NQ613BKrRrr9TTSLAabMD+1NxSwMqREBxup3zvk3H2vDeyoGo9z8XbQrntLULLUFWM d5k82YENHDqVpOna8PYdLo24w8xcFvx8Z7FF0cmviplF9WGK0sxPSjmZH0nf37eJv+L5 Y3aGwVdaw3t72b/VD+7MwExidtO4aWuf22zosktug71BXkhXw41mpyn7iPThLHT7upF4 goiyvWfQtRPNgtjJMhuiSN/WNPvH6dfNumh6TyZJ+broTm4wBEzuHAM3IjS5MOtcChRN 6AXw== X-Gm-Message-State: ALoCoQmQEKuQN0yBlB9/LdB6GlaRyTS47N8aoQEAt/FC3MywLroTWNIq16FfPskgCJmLw/slJLK4 X-Received: by 10.194.161.233 with SMTP id xv9mr1893903wjb.79.1386158112504; Wed, 04 Dec 2013 03:55:12 -0800 (PST) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginm.net. [82.1.113.198]) by mx.google.com with ESMTPSA id qc10sm6258318wic.9.2013.12.04.03.55.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Dec 2013 03:55:11 -0800 (PST) From: Will Newton To: qemu-devel@nongnu.org Date: Wed, 4 Dec 2013 11:54:59 +0000 Message-Id: <1386158099-9239-7-git-send-email-will.newton@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1386158099-9239-1-git-send-email-will.newton@linaro.org> References: <1386158099-9239-1-git-send-email-will.newton@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.212.175 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH v8 6/6] target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM instructions. Signed-off-by: Will Newton --- target-arm/translate.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) Changes in v8: - Use VFP helper instead of adding a NEON specific one - Drop size check diff --git a/target-arm/translate.c b/target-arm/translate.c index 9a8069e..73ed266 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4553,7 +4553,7 @@ static void gen_neon_narrow_op(int op, int u, int size, #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */ #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */ #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */ -#define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */ +#define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */ static const uint8_t neon_3r_sizes[] = { [NEON_3R_VHADD] = 0x7, @@ -4586,7 +4586,7 @@ static const uint8_t neon_3r_sizes[] = { [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */ [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */ [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */ - [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */ + [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */ }; /* Symbolic constants for op fields for Neon 2-register miscellaneous. @@ -4847,8 +4847,9 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins return 1; } break; - case NEON_3R_VRECPS_VRSQRTS: - if (u) { + case NEON_3R_FLOAT_MISC: + /* VMAXNM/VMINNM in ARMv8 */ + if (u && !arm_feature(env, ARM_FEATURE_V8)) { return 1; } break; @@ -5137,11 +5138,23 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins tcg_temp_free_ptr(fpstatus); break; } - case NEON_3R_VRECPS_VRSQRTS: - if (size == 0) - gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env); - else - gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env); + case NEON_3R_FLOAT_MISC: + if (u) { + /* VMAXNM/VMINNM */ + TCGv_ptr fpstatus = get_fpstatus_ptr(1); + if (size == 0) { + gen_helper_vfp_maxnms(tmp, tmp, tmp2, fpstatus); + } else { + gen_helper_vfp_minnms(tmp, tmp, tmp2, fpstatus); + } + tcg_temp_free_ptr(fpstatus); + } else { + if (size == 0) { + gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env); + } else { + gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env); + } + } break; case NEON_3R_VFM: {