From patchwork Tue Dec 3 21:51:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 296342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C38792C0097 for ; Wed, 4 Dec 2013 09:35:30 +1100 (EST) Received: from localhost ([::1]:45092 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vnxve-0007KC-RD for incoming@patchwork.ozlabs.org; Tue, 03 Dec 2013 16:54:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnxtV-0004lz-Gw for qemu-devel@nongnu.org; Tue, 03 Dec 2013 16:52:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VnxtP-0007oQ-SO for qemu-devel@nongnu.org; Tue, 03 Dec 2013 16:52:37 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:35990) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnxtP-0007nW-Jv for qemu-devel@nongnu.org; Tue, 03 Dec 2013 16:52:31 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VnxsD-0006IU-AE; Tue, 03 Dec 2013 21:51:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 3 Dec 2013 21:51:09 +0000 Message-Id: <1386107477-24165-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> References: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 81.2.115.146 Cc: patches@linaro.org, Michael Matz , Alexander Graf , C Fontana , Dirk Mueller , Laurent Desnogues , kvmarm@lists.cs.columbia.edu, Richard Henderson Subject: [Qemu-devel] [PATCH 04/12] target-arm: Support fp registers in gdb stub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Register the aarch64-fpu XML and implement the necessary read/write handlers so we can support reading and writing of FP registers in the gdb stub. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- configure | 2 +- gdb-xml/aarch64-fpu.xml | 86 +++++++++++++++++++++++++++++++++++++++++++++++ target-arm/helper.c | 48 +++++++++++++++++++++++++- 3 files changed, 134 insertions(+), 2 deletions(-) create mode 100644 gdb-xml/aarch64-fpu.xml diff --git a/configure b/configure index 3317013..c9ad1de 100755 --- a/configure +++ b/configure @@ -4401,7 +4401,7 @@ case "$target_name" in aarch64) TARGET_BASE_ARCH=arm bflt="yes" - gdb_xml_files="aarch64-core.xml" + gdb_xml_files="aarch64-core.xml aarch64-fpu.xml" ;; cris) ;; diff --git a/gdb-xml/aarch64-fpu.xml b/gdb-xml/aarch64-fpu.xml new file mode 100644 index 0000000..997197e --- /dev/null +++ b/gdb-xml/aarch64-fpu.xml @@ -0,0 +1,86 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target-arm/helper.c b/target-arm/helper.c index 263dbbf..73c97e8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -65,6 +65,48 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + /* 128 bit FP register */ + stfq_le_p(buf, env->vfp.regs[reg * 2]); + stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); + return 16; + case 32: + /* FPSR */ + stl_p(buf, vfp_get_fpsr(env)); + return 4; + case 33: + /* FPCR */ + stl_p(buf, vfp_get_fpcr(env)); + return 4; + default: + return 0; + } +} + +static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +{ + switch (reg) { + case 0 ... 31: + /* 128 bit FP register */ + env->vfp.regs[reg * 2] = ldfq_le_p(buf); + env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); + return 16; + case 32: + /* FPSR */ + vfp_set_fpsr(env, ldl_p(buf)); + return 4; + case 33: + /* FPCR */ + vfp_set_fpcr(env, ldl_p(buf)); + return 4; + default: + return 0; + } +} + static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -1785,7 +1827,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) CPUState *cs = CPU(cpu); CPUARMState *env = &cpu->env; - if (arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg, + aarch64_fpu_gdb_set_reg, + 34, "aarch64-fpu.xml", 0); + } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); } else if (arm_feature(env, ARM_FEATURE_VFP3)) {