From patchwork Tue Dec 3 08:48:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Fedorov X-Patchwork-Id: 296111 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0BAC82C009D for ; Tue, 3 Dec 2013 19:52:37 +1100 (EST) Received: from localhost ([::1]:40966 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vnlid-0004mO-7w for incoming@patchwork.ozlabs.org; Tue, 03 Dec 2013 03:52:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45193) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vnlfm-0001A4-8A for qemu-devel@nongnu.org; Tue, 03 Dec 2013 03:49:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vnlfa-000765-UB for qemu-devel@nongnu.org; Tue, 03 Dec 2013 03:49:38 -0500 Received: from mailout4.w1.samsung.com ([210.118.77.14]:36813) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vnlfa-00075V-O6 for qemu-devel@nongnu.org; Tue, 03 Dec 2013 03:49:26 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MX800EPA369IV30@mailout4.w1.samsung.com> for qemu-devel@nongnu.org; Tue, 03 Dec 2013 08:49:21 +0000 (GMT) X-AuditID: cbfec7f5-b7fd16d000007299-68-529d9b11c51b Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id C5.B2.29337.11B9D925; Tue, 03 Dec 2013 08:49:21 +0000 (GMT) Received: from s-fedorov.rnd.samsung.ru ([106.109.129.80]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MX800L8S361JP30@eusync1.samsung.com>; Tue, 03 Dec 2013 08:49:21 +0000 (GMT) From: Sergey Fedorov To: qemu-devel@nongnu.org Date: Tue, 03 Dec 2013 12:48:39 +0400 Message-id: <1386060535-15908-6-git-send-email-s.fedorov@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> References: <1386060535-15908-1-git-send-email-s.fedorov@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDJMWRmVeSWpSXmKPExsVy+t/xy7qCs+cGGazpZ7Z4e/knq8X6tsms FnPOPGCxON67g8WibddaFouHFzuZHdg8Ll7exepx59oeNo8n1zYzefRtWcUYwBLFZZOSmpNZ llqkb5fAldF3sIWx4L5MxelTD1kaGHeIdTFyckgImEjcmtnIBGGLSVy4t56ti5GLQ0hgKaPE x4MvWCGcfiaJT+eWglWxCehIzN53kRXEFhGQlPjddZoZpIhZYDWjxJttMxhBEsIC1hKT3naD 2SwCqhK79uwAKuLg4BVwlfjZHQxiSggoSMyZZANSwSngJnH82R2w8UJAFYcOHmCewMi7gJFh FaNoamlyQXFSeq6RXnFibnFpXrpecn7uJkZICH3dwbj0mNUhRgEORiUe3gl75gQJsSaWFVfm HmKU4GBWEuGdnz43SIg3JbGyKrUoP76oNCe1+BAjEwenVAPjvG6VWK+9G87Ov5owbfluhuSZ pye2dFism3ZYIPBCRwTHxf2LV4ZmObIciL7Bs8i9VTzzvrPE9sY7mn/fbUn1uaHOHfXyspBd yn1+fhbeZocFRx+LuQf9Kandvfau0nq1c1W1C4u5vmjPYnE3bl+XLHkrs+SV/K2+/xd1eJdk S+lInX7ONitXiaU4I9FQi7moOBEAL6hgj/8BAAA= X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 210.118.77.14 Cc: peter.maydell@linaro.org, Sergey Fedorov , a.basov@samsung.com, Svetlana Fedoseeva , johannes.winter@iaik.tugraz.at Subject: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Svetlana Fedoseeva Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM state info. Provide CPU mode name for monitor mode. Signed-off-by: Svetlana Fedoseeva Signed-off-by: Sergey Fedorov --- target-arm/cpu.h | 7 ++++--- target-arm/helper.c | 3 +++ target-arm/machine.c | 12 ++++++------ target-arm/translate.c | 2 +- 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0b93e39..94d8bd1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -124,9 +124,9 @@ typedef struct CPUARMState { uint32_t spsr; /* Banked registers. */ - uint32_t banked_spsr[6]; - uint32_t banked_r13[6]; - uint32_t banked_r14[6]; + uint32_t banked_spsr[7]; + uint32_t banked_r13[7]; + uint32_t banked_r14[7]; /* These hold r8-r12. */ uint32_t usr_regs[5]; @@ -402,6 +402,7 @@ enum arm_cpu_mode { ARM_CPU_MODE_FIQ = 0x11, ARM_CPU_MODE_IRQ = 0x12, ARM_CPU_MODE_SVC = 0x13, + ARM_CPU_MODE_MON = 0x16, ARM_CPU_MODE_ABT = 0x17, ARM_CPU_MODE_UND = 0x1b, ARM_CPU_MODE_SYS = 0x1f diff --git a/target-arm/helper.c b/target-arm/helper.c index d7922ad..d4407cf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2018,6 +2018,7 @@ static int bad_mode_switch(CPUARMState *env, int mode) case ARM_CPU_MODE_USR: case ARM_CPU_MODE_SYS: case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_MON: case ARM_CPU_MODE_ABT: case ARM_CPU_MODE_UND: case ARM_CPU_MODE_IRQ: @@ -2202,6 +2203,8 @@ int bank_number(int mode) return 4; case ARM_CPU_MODE_FIQ: return 5; + case ARM_CPU_MODE_MON: + return 6; } hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); } diff --git a/target-arm/machine.c b/target-arm/machine.c index 74f010f..51d0c79 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 13, - .minimum_version_id = 13, - .minimum_version_id_old = 13, + .version_id = 14, + .minimum_version_id = 14, + .minimum_version_id_old = 14, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -238,9 +238,9 @@ const VMStateDescription vmstate_arm_cpu = { .offset = 0, }, VMSTATE_UINT32(env.spsr, ARMCPU), - VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), + VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 7), + VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 7), + VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 7), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), /* The length-check must come before the arrays to avoid diff --git a/target-arm/translate.c b/target-arm/translate.c index 5f003e7..665c8ac 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10295,7 +10295,7 @@ void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb) } static const char *cpu_mode_names[16] = { - "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", + "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt", "???", "???", "???", "und", "???", "???", "???", "sys" };