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X-Received-From: 210.118.77.13 Cc: peter.maydell@linaro.org, a.basov@samsung.com, Sergey Fedorov , johannes.winter@iaik.tugraz.at Subject: [Qemu-devel] [RFC PATCH 13/21] target-arm: add SDER definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Sergey Fedorov --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5aeb630..ffc1b21 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -150,6 +150,7 @@ typedef struct CPUARMState { uint32_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint32_t c1_scr; /* secure config register. */ + uint32_t c1_sder; /* Secure debug enable register. */ uint32_t c1_nsacr; /* Non-secure access control register. */ uint32_t c2_base0; /* MMU translation table base 0. */ uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */ diff --git a/target-arm/helper.c b/target-arm/helper.c index b6d8a3c..780d0a0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1560,6 +1560,9 @@ static const ARMCPRegInfo tz_cp_reginfo[] = { .access = PL1_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), .resetvalue = 0 }, + { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) }, { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, .access = PL3_RW | PL2_R, .resetvalue = 0, .writefn = nsacr_write, .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) },