@@ -150,6 +150,7 @@ typedef struct CPUARMState {
uint32_t c1_coproc; /* Coprocessor access register. */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c1_scr; /* secure config register. */
+ uint32_t c1_sder; /* Secure debug enable register. */
uint32_t c1_nsacr; /* Non-secure access control register. */
uint32_t c2_base0; /* MMU translation table base 0. */
uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
@@ -1560,6 +1560,9 @@ static const ARMCPRegInfo tz_cp_reginfo[] = {
.access = PL1_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
.resetvalue = 0 },
+ { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1,
+ .access = PL3_RW, .resetvalue = 0,
+ .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) },
{ .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2,
.access = PL3_RW | PL2_R, .resetvalue = 0, .writefn = nsacr_write,
.fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) },
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com> --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ 2 files changed, 4 insertions(+)