From patchwork Mon Dec 2 20:12:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 295995 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7EA002C009F for ; Tue, 3 Dec 2013 07:29:40 +1100 (EST) Received: from localhost ([::1]:38737 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnZtp-00011q-Dv for incoming@patchwork.ozlabs.org; Mon, 02 Dec 2013 15:15:21 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnZrm-00070B-JR for qemu-devel@nongnu.org; Mon, 02 Dec 2013 15:13:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VnZrf-0003jC-9T for qemu-devel@nongnu.org; Mon, 02 Dec 2013 15:13:14 -0500 Received: from mail-wi0-f169.google.com ([209.85.212.169]:37067) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnZrf-0003ir-0C for qemu-devel@nongnu.org; Mon, 02 Dec 2013 15:13:07 -0500 Received: by mail-wi0-f169.google.com with SMTP id hn6so1000960wib.0 for ; Mon, 02 Dec 2013 12:13:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=W94w0NDch/wihRGCfuT0oqjkfVe67mCWXTOvbobo1yE=; b=PlK6zqtIvXOPTl5XQN6q/ThtPOZZOndHtOdU3qD1FNY3/a2wgd7ExGbpmYzfcTvevp 2l+fC6SFOwGI4u7fFyqJOMHz7LWBX12ZLPQFMSvxB/Va1C3hX7ns5fMi1k37jQQ0YzQ6 l6VGLY9I6WyksQf3JSfJ1sy+vOX9Y7QZ9NvbT45Py+coF0bPsZzFVb6T8OxDcyJ5+evg fWJpbbdZupzt5jefoeOgWAeiN36Y/GF5nVa6jKNuQEbo+3NiXSy8SLP4Ocurq65dAjon 036gxTZ6+NDhVe46qVx56WPIlhLEtxDQ+oXPGXgXUDIGGQMClnaNf+B8mL7ZLIaseeKw hYgA== X-Gm-Message-State: ALoCoQlyL18LOVwGGe0qKuZ3L8VI5jh0fGsWYcNVWWBNmZknnlgDBMlH3CyBVH0FXjowaZvwr6JZ X-Received: by 10.180.97.5 with SMTP id dw5mr19671461wib.42.1386015186279; Mon, 02 Dec 2013 12:13:06 -0800 (PST) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginm.net. [82.1.113.198]) by mx.google.com with ESMTPSA id e10sm103884524wiy.7.2013.12.02.12.13.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 02 Dec 2013 12:13:05 -0800 (PST) From: Will Newton To: qemu-devel@nongnu.org Date: Mon, 2 Dec 2013 20:12:53 +0000 Message-Id: <1386015177-6621-3-git-send-email-will.newton@linaro.org> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1386015177-6621-1-git-send-email-will.newton@linaro.org> References: <1386015177-6621-1-git-send-email-will.newton@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.212.169 Subject: [Qemu-devel] [PATCH v7 2/6] target-arm: Implement ARMv8 VSEL instruction. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds support for the VSEL floating point selection instruction which was added in ARMv8. Reviewed-by: Peter Maydell --- target-arm/translate.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 134 insertions(+), 1 deletion(-) Changes in v7: - Break out VSEL handling into a function - Properly sign extend VF and NF to 64bit - Use extract32 to decode insn - Fix brace style diff --git a/target-arm/translate.c b/target-arm/translate.c index f63e89d..0a22ad8 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2614,6 +2614,139 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size) return tmp; } +static int handle_vsel(uint32_t insn, uint32_t rd, uint32_t rn, uint32_t rm, + uint32_t dp) +{ + uint32_t cc = extract32(insn, 20, 2); + + if (dp) { + TCGv_i64 frn, frm, dest; + TCGv_i64 tmp, zero, zf, nf, vf; + + zero = tcg_const_i64(0); + + frn = tcg_temp_new_i64(); + frm = tcg_temp_new_i64(); + dest = tcg_temp_new_i64(); + + zf = tcg_temp_new_i64(); + nf = tcg_temp_new_i64(); + vf = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(zf, cpu_ZF); + tcg_gen_ext_i32_i64(nf, cpu_NF); + tcg_gen_ext_i32_i64(vf, cpu_VF); + + tcg_gen_ld_f64(frn, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f64(frm, cpu_env, vfp_reg_offset(dp, rm)); + switch (cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, + frn, frm); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, + frn, frm); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, + frn, frm); + tcg_temp_free_i64(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, + frn, frm); + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, + dest, frm); + tcg_temp_free_i64(tmp); + break; + } + tcg_gen_st_f64(dest, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(frn); + tcg_temp_free_i64(frm); + tcg_temp_free_i64(dest); + + tcg_temp_free_i64(zf); + tcg_temp_free_i64(nf); + tcg_temp_free_i64(vf); + + tcg_temp_free_i64(zero); + } else { + TCGv_i32 frn, frm, dest; + TCGv_i32 tmp, zero; + + zero = tcg_const_i32(0); + + frn = tcg_temp_new_i32(); + frm = tcg_temp_new_i32(); + dest = tcg_temp_new_i32(); + tcg_gen_ld_f32(frn, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f32(frm, cpu_env, vfp_reg_offset(dp, rm)); + switch (cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, + frn, frm); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, + frn, frm); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, + frn, frm); + tcg_temp_free_i32(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, + frn, frm); + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, + dest, frm); + tcg_temp_free_i32(tmp); + break; + } + tcg_gen_st_f32(dest, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(frn); + tcg_temp_free_i32(frm); + tcg_temp_free_i32(dest); + + tcg_temp_free_i32(zero); + } + + return 0; +} + +static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn) +{ + uint32_t rd, rn, rm, dp = extract32(insn, 8, 1); + + if (!arm_feature(env, ARM_FEATURE_V8)) { + return 1; + } + + if (dp) { + VFP_DREG_D(rd, insn); + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + } else { + rd = VFP_SREG_D(insn); + rn = VFP_SREG_N(insn); + rm = VFP_SREG_M(insn); + } + + if ((insn & 0x0f800e50) == 0x0e000a00) { + return handle_vsel(insn, rd, rn, rm, dp); + } + return 1; +} + /* Disassemble a VFP instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) @@ -2641,7 +2774,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) /* Encodings with T=1 (Thumb) or unconditional (ARM): * only used in v8 and above. */ - return 1; + return disas_vfp_v8_insn(env, s, insn); } dp = ((insn & 0xf00) == 0xb00);