From patchwork Fri Nov 29 02:59:59 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 295122 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EE6F22C00AA for ; Fri, 29 Nov 2013 15:12:38 +1100 (EST) Received: from localhost ([::1]:44948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmENA-0005EM-8Y for incoming@patchwork.ozlabs.org; Thu, 28 Nov 2013 22:04:04 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40028) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmELF-0002Rs-Sg for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VmELA-00024C-0v for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:02:05 -0500 Received: from mail-pd0-x229.google.com ([2607:f8b0:400e:c02::229]:42548) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VmEL9-000247-LC for qemu-devel@nongnu.org; Thu, 28 Nov 2013 22:01:59 -0500 Received: by mail-pd0-f169.google.com with SMTP id v10so13014955pde.14 for ; Thu, 28 Nov 2013 19:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=aiLxP6vbNCn5VwUnouVtsu/iAs85dAEx+E+vY14S3Mk=; b=YW/stHE5LR/54OrDoPDPBgZNtF20iSJz0ypYCoRB8q1Bqv4hCxywlB127b07Q4j/Mf 9g4kn7mvYKoBkz1/G0WTZR552ZiKPUa02rZeVPUfGLRE97MRjkDttJ5CiayqFaW3/ZQD 8P0sxzoxvVva/hJb9oOGgjXpMFFKH5ZsPsLPb3BMDwKXbXMp3LQGqIWzHFzyruoku98L qxFrYTDKZyBBNERJwv8cuL9tpiadC1mD3SAbxLxPQB2+R45J7pPPp/KdIL183lwb0Hbs iGVUGhs5GcINFxLPk1fuJJnK20kz+PZOlaOKdo4QAIUmZYkNgxZu/SaEPwjlskIC3Wxy t1xg== X-Received: by 10.68.217.129 with SMTP id oy1mr13686134pbc.23.1385694118706; Thu, 28 Nov 2013 19:01:58 -0800 (PST) Received: from pebble.twiddle.net.twiddle.net ([172.56.32.137]) by mx.google.com with ESMTPSA id hw10sm98475726pbc.24.2013.11.28.19.01.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Nov 2013 19:01:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 29 Nov 2013 15:59:59 +1300 Message-Id: <1385694047-6116-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1385694047-6116-1-git-send-email-rth@twiddle.net> References: <1385694047-6116-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c02::229 Subject: [Qemu-devel] [PATCH v2 12/60] target-i386: Remove gen_op_st_T0_A0 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Propagate its definition into all users. Signed-off-by: Richard Henderson --- target-i386/translate.c | 83 ++++++++++++++++++++++++------------------------- 1 file changed, 40 insertions(+), 43 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 268ed84..d3fc8f3 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -586,11 +586,6 @@ static inline void gen_op_st_v(DisasContext *s, int idx, TCGv t0, TCGv a0) tcg_gen_qemu_st_tl(t0, a0, s->mem_index, idx | MO_LE); } -static inline void gen_op_st_T0_A0(DisasContext *s, int idx) -{ - gen_op_st_v(s, idx, cpu_T[0], cpu_A0); -} - static inline void gen_op_st_T1_A0(DisasContext *s, int idx) { gen_op_st_v(s, idx, cpu_T[1], cpu_A0); @@ -599,7 +594,7 @@ static inline void gen_op_st_T1_A0(DisasContext *s, int idx) static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) { if (d == OR_TMP0) { - gen_op_st_T0_A0(s, idx); + gen_op_st_v(s, idx, cpu_T[0], cpu_A0); } else { gen_op_mov_reg_T0(idx, d); } @@ -801,7 +796,7 @@ static inline void gen_movs(DisasContext *s, int ot) gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); gen_string_movl_A0_EDI(s); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_ESI); gen_op_add_reg_T0(s->aflag, R_EDI); @@ -1226,7 +1221,7 @@ static inline void gen_stos(DisasContext *s, int ot) { gen_op_mov_TN_reg(MO_32, 0, R_EAX); gen_string_movl_A0_EDI(s); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); } @@ -1268,12 +1263,12 @@ static inline void gen_ins(DisasContext *s, int ot) /* Note: we must do this dummy write first to be restartable in case of page fault. */ gen_op_movl_T0_0(); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_mov_TN_reg(MO_16, 1, R_EDX); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]); tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff); gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_movl_T0_Dshift(ot); gen_op_add_reg_T0(s->aflag, R_EDI); if (use_icount) @@ -2250,7 +2245,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, if (is_store) { if (reg != OR_TMP0) gen_op_mov_TN_reg(ot, 0, reg); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } else { gen_op_ld_v(s, ot, cpu_T[0], cpu_A0); if (reg != OR_TMP0) @@ -2453,10 +2448,10 @@ static void gen_push_T0(DisasContext *s) gen_op_movq_A0_reg(R_ESP); if (s->dflag) { gen_op_addq_A0_im(-8); - gen_op_st_T0_A0(s, MO_64); + gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0); } else { gen_op_addq_A0_im(-2); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); } gen_op_mov_reg_A0(2, R_ESP); } else @@ -2477,7 +2472,7 @@ static void gen_push_T0(DisasContext *s) tcg_gen_mov_tl(cpu_T[1], cpu_A0); gen_op_addl_A0_seg(s, R_SS); } - gen_op_st_T0_A0(s, s->dflag + 1); + gen_op_st_v(s, s->dflag + 1, cpu_T[0], cpu_A0); if (s->ss32 && !s->addseg) gen_op_mov_reg_A0(1, R_ESP); else @@ -2497,7 +2492,7 @@ static void gen_push_T1(DisasContext *s) gen_op_st_T1_A0(s, MO_64); } else { gen_op_addq_A0_im(-2); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); } gen_op_mov_reg_A0(2, R_ESP); } else @@ -2582,7 +2577,7 @@ static void gen_pusha(DisasContext *s) gen_op_addl_A0_seg(s, R_SS); for(i = 0;i < 8; i++) { gen_op_mov_TN_reg(MO_32, 0, 7 - i); - gen_op_st_T0_A0(s, MO_16 + s->dflag); + gen_op_st_v(s, MO_16 + s->dflag, cpu_T[0], cpu_A0); gen_op_addl_A0_im(2 << s->dflag); } gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); @@ -2626,7 +2621,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) /* push bp */ gen_op_mov_TN_reg(MO_32, 0, R_EBP); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); if (level) { /* XXX: must save state */ gen_helper_enter64_level(cpu_env, tcg_const_i32(level), @@ -2651,7 +2646,7 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_addl_A0_seg(s, R_SS); /* push bp */ gen_op_mov_TN_reg(MO_32, 0, R_EBP); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); if (level) { /* XXX: must save state */ gen_helper_enter_level(cpu_env, tcg_const_i32(level), @@ -3223,7 +3218,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, xmm_regs[reg].XMM_L(0))); - gen_op_st_T0_A0(s, MO_32); + gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); } break; case 0x6e: /* movd mm, ea */ @@ -3475,7 +3470,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, if (mod != 3) { gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); - gen_op_st_T0_A0(s, MO_32); + gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); } else { rm = (modrm & 7) | REX_B(s); gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)), @@ -4890,7 +4885,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 2: /* not */ tcg_gen_not_tl(cpu_T[0], cpu_T[0]); if (mod != 3) { - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } else { gen_op_mov_reg_T0(ot, rm); } @@ -4898,7 +4893,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 3: /* neg */ tcg_gen_neg_tl(cpu_T[0], cpu_T[0]); if (mod != 3) { - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } else { gen_op_mov_reg_T0(ot, rm); } @@ -5311,7 +5306,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_mov_TN_reg(ot, 0, reg); gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); gen_op_addl_T0_T1(); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); gen_op_mov_reg_T1(ot, reg); } gen_op_update2_cc(); @@ -5570,10 +5565,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } val = insn_get(env, s, ot); gen_op_movl_T0_im(val); - if (mod != 3) - gen_op_st_T0_A0(s, ot); - else + if (mod != 3) { + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); + } else { gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s)); + } break; case 0x8a: case 0x8b: /* mov Ev, Gv */ @@ -5714,7 +5710,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_mov_reg_T0(ot, R_EAX); } else { gen_op_mov_TN_reg(ot, 0, R_EAX); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); } } break; @@ -5796,7 +5792,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (!(prefixes & PREFIX_LOCK)) gen_helper_lock(); gen_op_ld_v(s, ot, cpu_T[1], cpu_A0); - gen_op_st_T0_A0(s, ot); + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); if (!(prefixes & PREFIX_LOCK)) gen_helper_unlock(); gen_op_mov_reg_T1(ot, reg); @@ -6020,7 +6016,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 1: gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_32); + gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); break; case 2: gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env); @@ -6031,7 +6027,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, default: gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); break; } gen_helper_fpop(cpu_env); @@ -6041,12 +6037,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0: gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_32); + gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); break; case 1: gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_32); + gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); break; case 2: gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env); @@ -6057,7 +6053,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, default: gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); break; } if ((op & 7) == 3) @@ -6083,7 +6079,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x0f: /* fnstcw mem */ gen_helper_fnstcw(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); break; case 0x1d: /* fldt mem */ gen_update_cc_op(s); @@ -6109,7 +6105,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0x2f: /* fnstsw mem */ gen_helper_fnstsw(cpu_tmp2_i32, cpu_env); tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); break; case 0x3c: /* fbld */ gen_update_cc_op(s); @@ -7003,10 +6999,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } set_cc_op(s, CC_OP_SARB + ot); if (op != 0) { - if (mod != 3) - gen_op_st_T0_A0(s, ot); - else + if (mod != 3) { + gen_op_st_v(s, ot, cpu_T[0], cpu_A0); + } else { gen_op_mov_reg_T0(ot, rm); + } tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4); tcg_gen_movi_tl(cpu_cc_dst, 0); } @@ -7469,12 +7466,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base)); if (!s->dflag) gen_op_andl_T0_im(0xffffff); - gen_op_st_T0_A0(s, CODE64(s) + MO_32); + gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); break; case 1: if (mod == 3) { @@ -7532,12 +7529,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); - gen_op_st_T0_A0(s, MO_16); + gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base)); if (!s->dflag) gen_op_andl_T0_im(0xffffff); - gen_op_st_T0_A0(s, CODE64(s) + MO_32); + gen_op_st_v(s, CODE64(s) + MO_32, cpu_T[0], cpu_A0); } break; case 2: /* lgdt */ @@ -8008,7 +8005,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32); } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); - gen_op_st_T0_A0(s, MO_32); + gen_op_st_v(s, MO_32, cpu_T[0], cpu_A0); } break; case 5: /* lfence */