From patchwork Wed Nov 20 00:26:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Mammedov X-Patchwork-Id: 292614 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 287D92C012E for ; Wed, 20 Nov 2013 11:26:43 +1100 (EST) Received: from localhost ([::1]:52215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vivct-0005FD-P3 for incoming@patchwork.ozlabs.org; Tue, 19 Nov 2013 19:26:39 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33173) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vivca-0005E6-JM for qemu-devel@nongnu.org; Tue, 19 Nov 2013 19:26:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VivcV-0003t0-N7 for qemu-devel@nongnu.org; Tue, 19 Nov 2013 19:26:20 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47425) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VivcV-0003sw-Dd for qemu-devel@nongnu.org; Tue, 19 Nov 2013 19:26:15 -0500 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rAK0QESl031147 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Tue, 19 Nov 2013 19:26:14 -0500 Received: from thinkpad.redhat.com (vpn-227-134.phx2.redhat.com [10.3.227.134]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id rAK0QCsR011417; Tue, 19 Nov 2013 19:26:13 -0500 From: Igor Mammedov To: seabios@seabios.org Date: Wed, 20 Nov 2013 01:26:11 +0100 Message-Id: <1384907171-13249-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.25 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: qemu-devel@nongnu.org, kraxel@redhat.com, mst@redhat.com Subject: [Qemu-devel] [PATCH SeaBIOS v5] map 64-bit PCI BARs at location provided by emulator X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Currently 64-bit PCI BARs are unconditionally mapped by BIOS right over 4G + RamSizeOver4G location, which doesn't allow to reserve extra space before 64-bit PCI window. For memory hotplug an extra RAM space might be reserved after present 64-bit RAM end and BIOS should map 64-bit PCI BARs after it. Introduce "etc/reserved-memory-end" romfile to provide BIOS a hint where it should start mapping of 64-bit PCI BARs. If romfile is missing, BIOS reverts to legacy behavior and starts mapping after high memory. Signed-off-by: Igor Mammedov --- Corresponding QEMU patch is here: http://patchwork.ozlabs.org/patch/291417/ v4,5: * rebasing on top of current master v3: * s/pcimem64-start/reserved-memory-end/ v2: * place 64-bit window behind high RAM end if "etc/pcimem64-start" point below it. --- src/pciinit.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/pciinit.c b/src/pciinit.c index 7e63c5e..5aef8a6 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -15,6 +15,7 @@ #include "paravirt.h" // RamSize #include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR #include "list.h" // struct hlist_node +#include "byteorder.h" // le64_to_cpu /* PM Timer ticks per second (HZ) */ #define PM_TIMER_FREQUENCY 3579545 @@ -762,6 +763,15 @@ static void pci_bios_map_devices(struct pci_bus *busses) { if (pci_bios_init_root_regions(busses)) { struct pci_region r64_mem, r64_pref; + u64 ram64_end = 0x100000000ULL + RamSizeOver4G; + u64 base64 = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", + ram64_end)); + if (base64 < ram64_end) { + dprintf(1, "ignorig etc/reserved-memory-end [0x%llx] below present" + " RAM, placing 64-bit PCI window behind RAM end: %llx", + base64, ram64_end); + base64 = ram64_end; + } r64_mem.list.first = NULL; r64_pref.list.first = NULL; pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM], @@ -777,7 +787,7 @@ static void pci_bios_map_devices(struct pci_bus *busses) u64 align_mem = pci_region_align(&r64_mem); u64 align_pref = pci_region_align(&r64_pref); - r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem); + r64_mem.base = ALIGN(base64, align_mem); r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref); pcimem64_start = r64_mem.base; pcimem64_end = r64_pref.base + sum_pref;