From patchwork Tue Nov 19 06:18:10 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 292307 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9F87D2C00C2 for ; Tue, 19 Nov 2013 17:55:15 +1100 (EST) Received: from localhost ([::1]:47309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViedK-0000X0-Jr for incoming@patchwork.ozlabs.org; Tue, 19 Nov 2013 01:17:58 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49865) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Viecf-0008SY-9D for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ViecZ-0004l8-Db for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:17 -0500 Received: from mail-pa0-f47.google.com ([209.85.220.47]:34780) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViecZ-0004kx-4V for qemu-devel@nongnu.org; Tue, 19 Nov 2013 01:17:11 -0500 Received: by mail-pa0-f47.google.com with SMTP id kq14so3280118pab.6 for ; Mon, 18 Nov 2013 22:17:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fr6AP5HnwbrCqsFrNPMx+2nvau28PRlIZsPoM8PRugY=; b=hq6xsMwkYoD0ya6XY6LEIu/fgCtqCo2PWNsndGKvEEZ9p25UqDtn9Fsx0o14ThYeHW dGwz1cYkJrcJZ2mEWVwhMoargx9InWKeOnOyd4uOwMebxgv0//E2bYERcaNmQ2HYpYM3 vFYqw6RUaPb3xTuY+cRPshALxeXG154r3FaK6ap4GxkVoCR8JeALgAgXsSR+zm7uD+VO lMt3trsAghbuecxG3CNV8fMH7WOFw0KMt9dn1Tsx/N16zEbR65dEtTwXHJ8XI4jkztlY b8r3lomdwu9Kw79H4IqSp+a5zwPasrPQy9MnlZVjW7DjIeOk2m1RGQBKiAnWEBGPmIbD Wm0A== X-Gm-Message-State: ALoCoQlNHvINimclhlb/4hroFkDX2hM1LOSWoEEeTJQyeYuSmRyeYlnheRetDxPBs52cHzlATUEw X-Received: by 10.66.248.202 with SMTP id yo10mr10279pac.177.1384841830508; Mon, 18 Nov 2013 22:17:10 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id rz6sm19165159pab.22.2013.11.18.22.17.08 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 18 Nov 2013 22:17:09 -0800 (PST) From: Christoffer Dall To: qemu-devel@nongnu.org Date: Mon, 18 Nov 2013 22:18:10 -0800 Message-Id: <1384841896-19566-5-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> References: <1384841896-19566-1-git-send-email-christoffer.dall@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.47 Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Subject: [Qemu-devel] [RFC PATCH v3 04/10] arm_gic: Support setting/getting binary point reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well. Signed-off-by: Christoffer Dall Changelog [v3]: - Treat writes for GIC prior to v2 as RAZ/WI. Changelog [v2]: - Renamed binary_point to bpr and abpr - Added GICC_ABPR read-as-write logic for TCG Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 12 +++++++++--- hw/intc/arm_gic_common.c | 6 ++++-- include/hw/intc/arm_gic_common.h | 7 +++++++ 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 2ed9a1a..73acf62 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -587,8 +587,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x04: /* Priority mask */ return s->priority_mask[cpu]; case 0x08: /* Binary Point */ - /* ??? Not implemented. */ - return 0; + return s->bpr[cpu]; case 0x0c: /* Acknowledge */ value = gic_acknowledge_irq(s, cpu); value |= (GIC_SGI_SRC(value, cpu) & 0x7) << 10; @@ -597,6 +596,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) return s->running_priority[cpu]; case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; + case 0x1c: /* Aliased Binary Point */ + return s->abpr[cpu]; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); @@ -615,10 +616,15 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->priority_mask[cpu] = (value & 0xff); break; case 0x08: /* Binary Point */ - /* ??? Not implemented. */ + s->bpr[cpu] = (value & 0x7); break; case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff); + case 0x1c: /* Aliased Binary Point */ + if (s->revision >= 2) { + s->abpr[cpu] = (value & 0x7); + } + break; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index d1a1b0f..6fbdafc 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = { static const VMStateDescription vmstate_gic = { .name = "arm_gic", - .version_id = 5, - .minimum_version_id = 5, + .version_id = 6, + .minimum_version_id = 6, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { @@ -76,6 +76,8 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_irq, GICState, GIC_NCPU), VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU), + VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU), + VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU), VMSTATE_END_OF_LIST() } }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index e19481b..120d6b2 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -62,6 +62,13 @@ typedef struct GICState { uint16_t running_priority[GIC_NCPU]; uint16_t current_pending[GIC_NCPU]; + /* We present the GICv2 without security extensions to a guest and + * therefore the guest can configure the GICC_CTLR to configure group 1 + * binary point in the abpr. + */ + uint8_t bpr[GIC_NCPU]; + uint8_t abpr[GIC_NCPU]; + uint32_t num_cpu; MemoryRegion iomem; /* Distributor */