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[138.130.249.46]) by mx.google.com with ESMTPSA id xs1sm1726198pac.7.2013.11.06.17.07.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Nov 2013 17:07:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Nov 2013 11:05:03 +1000 Message-Id: <1383786324-18415-41-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1383786324-18415-1-git-send-email-rth@twiddle.net> References: <1383786324-18415-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22d Subject: [Qemu-devel] [PATCH for-1.8 40/61] target-i386: Combine gen_push_T* into gen_push_v X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Reduce ifdefs, share more code between paths, reduce the number of TCG ops generated. Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case. Signed-off-by: Richard Henderson --- target-i386/translate.c | 106 +++++++++++++++--------------------------------- 1 file changed, 32 insertions(+), 74 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index c560d56..77ed32e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2387,78 +2387,36 @@ static inline void gen_stack_update(DisasContext *s, int addend) } } -/* generate a push. It depends on ss32, addseg and dflag */ -static void gen_push_T0(DisasContext *s) +/* Generate a push. It depends on ss32, addseg and dflag. */ +static void gen_push_v(DisasContext *s, TCGv val) { -#ifdef TARGET_X86_64 - if (CODE64(s)) { - gen_op_movq_A0_reg(R_ESP); - if (s->dflag != MO_16) { - gen_op_addq_A0_im(-8); - gen_op_st_v(s, MO_64, cpu_T[0], cpu_A0); - } else { - gen_op_addq_A0_im(-2); - gen_op_st_v(s, MO_16, cpu_T[0], cpu_A0); - } - gen_op_mov_reg_A0(MO_64, R_ESP); - } else -#endif - { - gen_op_movl_A0_reg(R_ESP); - gen_op_addl_A0_im(-1 << s->dflag); - if (s->ss32) { - if (s->addseg) { - tcg_gen_mov_tl(cpu_T[1], cpu_A0); - gen_op_addl_A0_seg(s, R_SS); - } - } else { - tcg_gen_ext16u_tl(cpu_A0, cpu_A0); - tcg_gen_mov_tl(cpu_T[1], cpu_A0); - gen_op_addl_A0_seg(s, R_SS); - } - gen_op_st_v(s, s->dflag, cpu_T[0], cpu_A0); - if (s->ss32 && !s->addseg) - gen_op_mov_reg_A0(MO_32, R_ESP); - else - gen_op_mov_reg_T1(MO_16 + s->ss32, R_ESP); - } -} + TCGMemOp a_ot, d_ot = mo_pushpop(s, s->dflag); + int size = 1 << d_ot; + TCGv new_esp = cpu_A0; + + tcg_gen_subi_tl(cpu_A0, cpu_regs[R_ESP], size); -/* generate a push. It depends on ss32, addseg and dflag */ -/* slower version for T1, only used for call Ev */ -static void gen_push_T1(DisasContext *s) -{ -#ifdef TARGET_X86_64 if (CODE64(s)) { - gen_op_movq_A0_reg(R_ESP); - if (s->dflag != MO_16) { - gen_op_addq_A0_im(-8); - gen_op_st_v(s, MO_64, cpu_T[1], cpu_A0); - } else { - gen_op_addq_A0_im(-2); - gen_op_st_v(s, MO_16, cpu_T[1], cpu_A0); - } - gen_op_mov_reg_A0(MO_64, R_ESP); - } else -#endif - { - gen_op_movl_A0_reg(R_ESP); - gen_op_addl_A0_im(-1 << s->dflag); - if (s->ss32) { - if (s->addseg) { - gen_op_addl_A0_seg(s, R_SS); - } - } else { - tcg_gen_ext16u_tl(cpu_A0, cpu_A0); + a_ot = MO_64; + } else if (s->ss32) { + a_ot = MO_32; + if (s->addseg) { + new_esp = cpu_tmp4; + tcg_gen_mov_tl(new_esp, cpu_A0); gen_op_addl_A0_seg(s, R_SS); + } else { + tcg_gen_ext32u_tl(cpu_A0, cpu_A0); } - gen_op_st_v(s, s->dflag, cpu_T[1], cpu_A0); - - if (s->ss32 && !s->addseg) - gen_op_mov_reg_A0(MO_32, R_ESP); - else - gen_stack_update(s, -1 << s->dflag); + } else { + a_ot = MO_16; + new_esp = cpu_tmp4; + tcg_gen_ext16u_tl(cpu_A0, cpu_A0); + tcg_gen_mov_tl(new_esp, cpu_A0); + gen_op_addl_A0_seg(s, R_SS); } + + gen_op_st_v(s, d_ot, val, cpu_A0); + gen_op_mov_reg_v(a_ot, R_ESP, new_esp); } /* two step pop is necessary for precise exceptions */ @@ -4986,7 +4944,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } next_eip = s->pc - s->cs_base; tcg_gen_movi_tl(cpu_T[1], next_eip); - gen_push_T1(s); + gen_push_v(s, cpu_T[1]); gen_op_jmp_T0(); gen_eob(s); break; @@ -5036,7 +4994,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_eob(s); break; case 6: /* push Ev */ - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); break; default: goto illegal_op; @@ -5278,7 +5236,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* push/pop */ case 0x50 ... 0x57: /* push */ gen_op_mov_TN_reg(MO_32, 0, (b & 7) | REX_B(s)); - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); break; case 0x58 ... 0x5f: /* pop */ ot = mo_pushpop(s, dflag); @@ -5305,7 +5263,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, else val = (int8_t)insn_get(env, s, MO_8); tcg_gen_movi_tl(cpu_T[0], val); - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); break; case 0x8f: /* pop Ev */ ot = mo_pushpop(s, dflag); @@ -5358,12 +5316,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (CODE64(s)) goto illegal_op; gen_op_movl_T0_seg(b >> 3); - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); break; case 0x1a0: /* push fs */ case 0x1a8: /* push gs */ gen_op_movl_T0_seg((b >> 3) & 7); - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); break; case 0x07: /* pop es */ case 0x17: /* pop ss */ @@ -6512,7 +6470,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, tval &= 0xffffffff; } tcg_gen_movi_tl(cpu_T[0], next_eip); - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); gen_jmp(s, tval); } break; @@ -6608,7 +6566,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } else { gen_update_cc_op(s); gen_helper_read_eflags(cpu_T[0], cpu_env); - gen_push_T0(s); + gen_push_v(s, cpu_T[0]); } break; case 0x9d: /* popf */