| Message ID | 1380276614-857-3-git-send-email-m.hamayun@virtualopensystems.com |
|---|---|
| State | New |
| Headers | show |
Hi, Am 27.09.2013 12:10, schrieb Mian M. Hamayun: > From: John Rigby <john.rigby@linaro.org> > > Just an copy of a15 with a57 substituting a15 for now. > > Signed-off-by: John Rigby <john.rigby@linaro.org> > Signed-off-by: Mian M. Hamayun <m.hamayun@virtualopensystems.com> > --- > hw/cpu/Makefile.objs | 1 + > hw/cpu/a57mpcore.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++++++ > target-arm/cpu.c | 9 ++++ > 3 files changed, 132 insertions(+) > create mode 100644 hw/cpu/a57mpcore.c I had previously gently nack'ed this patch - conversions are still queued on qom-next currently though. Having PMM's kernel load patches now, I'll try if I can still get this posted today. In particular use of QOM realize and embedding of child device with avoidance of child instantiation during realization. Regards, Andreas > > diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs > index df287c1..22e9567 100644 > --- a/hw/cpu/Makefile.objs > +++ b/hw/cpu/Makefile.objs > @@ -1,5 +1,6 @@ > obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o > obj-$(CONFIG_A9MPCORE) += a9mpcore.o > obj-$(CONFIG_A15MPCORE) += a15mpcore.o > +obj-$(CONFIG_A57MPCORE) += a57mpcore.o > obj-$(CONFIG_ICC_BUS) += icc_bus.o > > diff --git a/hw/cpu/a57mpcore.c b/hw/cpu/a57mpcore.c > new file mode 100644 > index 0000000..4be277f > --- /dev/null > +++ b/hw/cpu/a57mpcore.c > @@ -0,0 +1,122 @@ > +/* > + * Cortex-A57MPCore internal peripheral emulation. > + * > + * Copyright (c) 2012 Linaro Limited. > + * Written by Peter Maydell. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +#include "hw/sysbus.h" > +#include "sysemu/kvm.h" > + > +/* A57MP private memory region. */ > + > +#define TYPE_A57MPCORE_PRIV "a57mpcore_priv" > +#define A57MPCORE_PRIV(obj) \ > + OBJECT_CHECK(A57MPPrivState, (obj), TYPE_A57MPCORE_PRIV) > + > +typedef struct A57MPPrivState { > + /*< private >*/ > + SysBusDevice parent_obj; > + /*< public >*/ > + > + uint32_t num_cpu; > + uint32_t num_irq; > + MemoryRegion container; > + DeviceState *gic; > +} A57MPPrivState; > + > +static void a57mp_priv_set_irq(void *opaque, int irq, int level) > +{ > + A57MPPrivState *s = (A57MPPrivState *)opaque; > + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); > +} > + > +static int a57mp_priv_init(SysBusDevice *dev) > +{ > + A57MPPrivState *s = A57MPCORE_PRIV(dev); > + SysBusDevice *busdev; > + const char *gictype = "arm_gic"; > + > + if (kvm_irqchip_in_kernel()) { > + gictype = "kvm-arm-gic"; > + } > + > + s->gic = qdev_create(NULL, gictype); > + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); > + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); > + qdev_prop_set_uint32(s->gic, "revision", 2); > + qdev_init_nofail(s->gic); > + busdev = SYS_BUS_DEVICE(s->gic); > + > + /* Pass through outbound IRQ lines from the GIC */ > + sysbus_pass_irq(dev, busdev); > + > + /* Pass through inbound GPIO lines to the GIC */ > + qdev_init_gpio_in(DEVICE(dev), a57mp_priv_set_irq, s->num_irq - 32); > + > + /* Memory map (addresses are offsets from PERIPHBASE): > + * 0x0000-0x0fff -- reserved > + * 0x1000-0x1fff -- GIC Distributor > + * 0x2000-0x2fff -- GIC CPU interface > + * 0x4000-0x4fff -- GIC virtual interface control (not modelled) > + * 0x5000-0x5fff -- GIC virtual interface control (not modelled) > + * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) > + */ > + memory_region_init(&s->container, OBJECT(s), > + "a57mp-priv-container", 0x8000); > + memory_region_add_subregion(&s->container, 0x1000, > + sysbus_mmio_get_region(busdev, 0)); > + memory_region_add_subregion(&s->container, 0x2000, > + sysbus_mmio_get_region(busdev, 1)); > + > + sysbus_init_mmio(dev, &s->container); > + return 0; > +} > + > +static Property a57mp_priv_properties[] = { > + DEFINE_PROP_UINT32("num-cpu", A57MPPrivState, num_cpu, 1), > + /* The Cortex-A57MP may have anything from 0 to 224 external interrupt > + * IRQ lines (with another 32 internal). We default to 128+32, which > + * is the number provided by the Cortex-A57MP test chip in the > + * Versatile Express A57 development board. > + * Other boards may differ and should set this property appropriately. > + */ > + DEFINE_PROP_UINT32("num-irq", A57MPPrivState, num_irq, 160), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static void a57mp_priv_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); > + k->init = a57mp_priv_init; > + dc->props = a57mp_priv_properties; > + /* We currently have no savable state */ > +} > + > +static const TypeInfo a57mp_priv_info = { > + .name = TYPE_A57MPCORE_PRIV, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(A57MPPrivState), > + .class_init = a57mp_priv_class_init, > +}; > + > +static void a57mp_register_types(void) > +{ > + type_register_static(&a57mp_priv_info); > +} > + > +type_init(a57mp_register_types) > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index d40f2a7..5d811b9 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -684,6 +684,14 @@ static void cortex_a15_initfn(Object *obj) > define_arm_cp_regs(cpu, cortexa15_cp_reginfo); > } > > +static void cortex_a57_initfn(Object *obj) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + set_feature(&cpu->env, ARM_FEATURE_V8); > + set_feature(&cpu->env, ARM_FEATURE_AARCH64); > + /* TODO: See if we need to set some more features for ARMv8 ? */ > +} > + > static void ti925t_initfn(Object *obj) > { > ARMCPU *cpu = ARM_CPU(obj); > @@ -872,6 +880,7 @@ static const ARMCPUInfo arm_cpus[] = { > { .name = "cortex-a8", .initfn = cortex_a8_initfn }, > { .name = "cortex-a9", .initfn = cortex_a9_initfn }, > { .name = "cortex-a15", .initfn = cortex_a15_initfn }, > + { .name = "cortex-a57", .initfn = cortex_a57_initfn }, > { .name = "ti925t", .initfn = ti925t_initfn }, > { .name = "sa1100", .initfn = sa1100_initfn }, > { .name = "sa1110", .initfn = sa1110_initfn }, >
On 28 September 2013 00:53, Andreas Färber <afaerber@suse.de> wrote: > Hi, > > Am 27.09.2013 12:10, schrieb Mian M. Hamayun: >> From: John Rigby <john.rigby@linaro.org> >> >> Just an copy of a15 with a57 substituting a15 for now. > I had previously gently nack'ed this patch - conversions are still > queued on qom-next currently though. Having PMM's kernel load patches > now, I'll try if I can still get this posted today. It's also already had a strong nak from me because it's not really an A57 model. We should be using 'cpu host' until there's a public TRM for a real A57 model. -- PMM
On 28/09/2013 02:16, Peter Maydell wrote: > On 28 September 2013 00:53, Andreas Färber <afaerber@suse.de> wrote: >> Hi, >> >> Am 27.09.2013 12:10, schrieb Mian M. Hamayun: >>> From: John Rigby <john.rigby@linaro.org> >>> >>> Just an copy of a15 with a57 substituting a15 for now. >> I had previously gently nack'ed this patch - conversions are still >> queued on qom-next currently though. Having PMM's kernel load patches >> now, I'll try if I can still get this posted today. > It's also already had a strong nak from me because it's not > really an A57 model. We should be using 'cpu host' > until there's a public TRM for a real A57 model. > > -- PMM I agree with your concerns and feedback but as I remember from our last KVM/ARM telco, we agreed that I should not wait for the -cpu host support to become available and post the next patch series anyways. Also there are multiple patches under review for providing the -cpu host or equivalent support in QEMU and/or KVM such as the one posted by Peter Maydell and another CPU=Host patch from Anup Patel. We will update our patch series, once we have consensus on which implementation to actually use for providing the -cpu host support. -- Hamayun
Am 30.09.2013 17:53, schrieb Mian M. Hamayun: > On 28/09/2013 02:16, Peter Maydell wrote: >> On 28 September 2013 00:53, Andreas Färber <afaerber@suse.de> wrote: >>> Am 27.09.2013 12:10, schrieb Mian M. Hamayun: >>>> From: John Rigby <john.rigby@linaro.org> >>>> >>>> Just an copy of a15 with a57 substituting a15 for now. >>> I had previously gently nack'ed this patch - conversions are still >>> queued on qom-next currently though. Having PMM's kernel load patches >>> now, I'll try if I can still get this posted today. >> It's also already had a strong nak from me because it's not >> really an A57 model. We should be using 'cpu host' >> until there's a public TRM for a real A57 model. > > I agree with your concerns and feedback but as I remember from our last > KVM/ARM telco, we agreed that I should not wait for the -cpu host support > to become available and post the next patch series anyways. In such a case please use "RFC" rather than "PATCH" to clarify that it is known not yet ready for applying. :-) Andreas > Also there are multiple patches under review for providing the -cpu host > or equivalent support in QEMU and/or KVM such as the one posted by Peter > Maydell and another CPU=Host patch from Anup Patel. We will update our > patch > series, once we have consensus on which implementation to actually use for > providing the -cpu host support. > > -- > Hamayun
On 1 October 2013 00:53, Mian M. Hamayun <m.hamayun@virtualopensystems.com> wrote: > Also there are multiple patches under review for providing the -cpu host > or equivalent support in QEMU and/or KVM such as the one posted by Peter > Maydell and another CPU=Host patch from Anup Patel. Yeah, I agree it's a bit up in the air at the moment API wise but I think we've more or less converged on a decision. https://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/aarch64-kvm has the QEMU side stuff as I currently have it, and it doesn't depend on the kernel patches being committed. -- PMM
diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs index df287c1..22e9567 100644 --- a/hw/cpu/Makefile.objs +++ b/hw/cpu/Makefile.objs @@ -1,5 +1,6 @@ obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o obj-$(CONFIG_A9MPCORE) += a9mpcore.o obj-$(CONFIG_A15MPCORE) += a15mpcore.o +obj-$(CONFIG_A57MPCORE) += a57mpcore.o obj-$(CONFIG_ICC_BUS) += icc_bus.o diff --git a/hw/cpu/a57mpcore.c b/hw/cpu/a57mpcore.c new file mode 100644 index 0000000..4be277f --- /dev/null +++ b/hw/cpu/a57mpcore.c @@ -0,0 +1,122 @@ +/* + * Cortex-A57MPCore internal peripheral emulation. + * + * Copyright (c) 2012 Linaro Limited. + * Written by Peter Maydell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "hw/sysbus.h" +#include "sysemu/kvm.h" + +/* A57MP private memory region. */ + +#define TYPE_A57MPCORE_PRIV "a57mpcore_priv" +#define A57MPCORE_PRIV(obj) \ + OBJECT_CHECK(A57MPPrivState, (obj), TYPE_A57MPCORE_PRIV) + +typedef struct A57MPPrivState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + uint32_t num_cpu; + uint32_t num_irq; + MemoryRegion container; + DeviceState *gic; +} A57MPPrivState; + +static void a57mp_priv_set_irq(void *opaque, int irq, int level) +{ + A57MPPrivState *s = (A57MPPrivState *)opaque; + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); +} + +static int a57mp_priv_init(SysBusDevice *dev) +{ + A57MPPrivState *s = A57MPCORE_PRIV(dev); + SysBusDevice *busdev; + const char *gictype = "arm_gic"; + + if (kvm_irqchip_in_kernel()) { + gictype = "kvm-arm-gic"; + } + + s->gic = qdev_create(NULL, gictype); + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_prop_set_uint32(s->gic, "revision", 2); + qdev_init_nofail(s->gic); + busdev = SYS_BUS_DEVICE(s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(dev, busdev); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(DEVICE(dev), a57mp_priv_set_irq, s->num_irq - 32); + + /* Memory map (addresses are offsets from PERIPHBASE): + * 0x0000-0x0fff -- reserved + * 0x1000-0x1fff -- GIC Distributor + * 0x2000-0x2fff -- GIC CPU interface + * 0x4000-0x4fff -- GIC virtual interface control (not modelled) + * 0x5000-0x5fff -- GIC virtual interface control (not modelled) + * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) + */ + memory_region_init(&s->container, OBJECT(s), + "a57mp-priv-container", 0x8000); + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(busdev, 0)); + memory_region_add_subregion(&s->container, 0x2000, + sysbus_mmio_get_region(busdev, 1)); + + sysbus_init_mmio(dev, &s->container); + return 0; +} + +static Property a57mp_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", A57MPPrivState, num_cpu, 1), + /* The Cortex-A57MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 128+32, which + * is the number provided by the Cortex-A57MP test chip in the + * Versatile Express A57 development board. + * Other boards may differ and should set this property appropriately. + */ + DEFINE_PROP_UINT32("num-irq", A57MPPrivState, num_irq, 160), + DEFINE_PROP_END_OF_LIST(), +}; + +static void a57mp_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + k->init = a57mp_priv_init; + dc->props = a57mp_priv_properties; + /* We currently have no savable state */ +} + +static const TypeInfo a57mp_priv_info = { + .name = TYPE_A57MPCORE_PRIV, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A57MPPrivState), + .class_init = a57mp_priv_class_init, +}; + +static void a57mp_register_types(void) +{ + type_register_static(&a57mp_priv_info); +} + +type_init(a57mp_register_types) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d40f2a7..5d811b9 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -684,6 +684,14 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } +static void cortex_a57_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + /* TODO: See if we need to set some more features for ARMv8 ? */ +} + static void ti925t_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -872,6 +880,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn }, + { .name = "cortex-a57", .initfn = cortex_a57_initfn }, { .name = "ti925t", .initfn = ti925t_initfn }, { .name = "sa1100", .initfn = sa1100_initfn }, { .name = "sa1110", .initfn = sa1110_initfn },