From patchwork Sun Jun 16 15:57:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 251705 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8E7972C0096 for ; Mon, 17 Jun 2013 02:08:07 +1000 (EST) Received: from localhost ([::1]:57893 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UoFUr-0003Bs-I9 for incoming@patchwork.ozlabs.org; Sun, 16 Jun 2013 12:08:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42629) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UoFLX-0007VY-Nr for qemu-devel@nongnu.org; Sun, 16 Jun 2013 11:58:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UoFLU-0007AG-Ng for qemu-devel@nongnu.org; Sun, 16 Jun 2013 11:58:27 -0400 Received: from cantor2.suse.de ([195.135.220.15]:60043 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UoFLU-00079p-BG for qemu-devel@nongnu.org; Sun, 16 Jun 2013 11:58:24 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id BECE4A41E0 for ; Sun, 16 Jun 2013 17:58:23 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 16 Jun 2013 17:57:45 +0200 Message-Id: <1371398269-6213-26-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1371398269-6213-1-git-send-email-afaerber@suse.de> References: <1371398269-6213-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH qom-cpu v2 25/29] cpu: Move CPU_INTERRUPT_* to qom/cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Turn them into an enum. Un-poison them but make CPU_INTERRUPT_TGT_* only available to CONFIG_SOFTMMU and CONFIG_USER_ONLY, i.e., not to devices. Signed-off-by: Andreas Färber --- include/exec/cpu-all.h | 50 ------------------------------------------- include/exec/poison.h | 13 ------------ include/qom/cpu.h | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+), 63 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6499cd0..5d7d8a6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -357,56 +357,6 @@ CPUArchState *cpu_copy(CPUArchState *env); void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...) GCC_FMT_ATTR(2, 3); -/* Flags for use in ENV->INTERRUPT_PENDING. - - The numbers assigned here are non-sequential in order to preserve - binary compatibility with the vmstate dump. Bit 0 (0x0001) was - previously used for CPU_INTERRUPT_EXIT, and is cleared when loading - the vmstate dump. */ - -/* External hardware interrupt pending. This is typically used for - interrupts from devices. */ -#define CPU_INTERRUPT_HARD 0x0002 - -/* Exit the current TB. This is typically used when some system-level device - makes some change to the memory mapping. E.g. the a20 line change. */ -#define CPU_INTERRUPT_EXITTB 0x0004 - -/* Halt the CPU. */ -#define CPU_INTERRUPT_HALT 0x0020 - -/* Debug event pending. */ -#define CPU_INTERRUPT_DEBUG 0x0080 - -/* Several target-specific external hardware interrupts. Each target/cpu.h - should define proper names based on these defines. */ -#define CPU_INTERRUPT_TGT_EXT_0 0x0008 -#define CPU_INTERRUPT_TGT_EXT_1 0x0010 -#define CPU_INTERRUPT_TGT_EXT_2 0x0040 -#define CPU_INTERRUPT_TGT_EXT_3 0x0200 -#define CPU_INTERRUPT_TGT_EXT_4 0x1000 - -/* Several target-specific internal interrupts. These differ from the - preceding target-specific interrupts in that they are intended to - originate from within the cpu itself, typically in response to some - instruction being executed. These, therefore, are not masked while - single-stepping within the debugger. */ -#define CPU_INTERRUPT_TGT_INT_0 0x0100 -#define CPU_INTERRUPT_TGT_INT_1 0x0400 -#define CPU_INTERRUPT_TGT_INT_2 0x0800 -#define CPU_INTERRUPT_TGT_INT_3 0x2000 - -/* First unused bit: 0x4000. */ - -/* The set of all bits that should be masked when single-stepping. */ -#define CPU_INTERRUPT_SSTEP_MASK \ - (CPU_INTERRUPT_HARD \ - | CPU_INTERRUPT_TGT_EXT_0 \ - | CPU_INTERRUPT_TGT_EXT_1 \ - | CPU_INTERRUPT_TGT_EXT_2 \ - | CPU_INTERRUPT_TGT_EXT_3 \ - | CPU_INTERRUPT_TGT_EXT_4) - /* Breakpoint/watchpoint flags */ #define BP_MEM_READ 0x01 #define BP_MEM_WRITE 0x02 diff --git a/include/exec/poison.h b/include/exec/poison.h index 2341a75..00caabe 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -46,18 +46,5 @@ #pragma GCC poison stl_phys #pragma GCC poison stq_phys -#pragma GCC poison CPU_INTERRUPT_HARD -#pragma GCC poison CPU_INTERRUPT_EXITTB -#pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 - #endif #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 467896c..ca917d8 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -375,6 +375,63 @@ CPUState *qemu_get_cpu(int index); */ bool cpu_exists(int64_t id); +/** + * CPUInterruptFlags: + * @CPU_INTERRUPT_HARD: External hardware interrupt pending. + * This is typically used for interrupts from devices. + * @CPU_INTERRUPT_EXITTB: Exit the current TB. + * This is typically used when some system-level device makes some change + * to the memory mapping. E.g., the a20 line change. + * @CPU_INTERRUPT_HALT: Halt the CPU. + * @CPU_INTERRUPT_DEBUG: Debug event pending. + * @CPU_INTERRUPT_SSTEP_MASK: The set of all bits that should be masked + * when single-stepping. + * + * Flags for #CPUState.interrupt_pending. + * + * The numbers assigned here are non-sequential in order to preserve + * binary compatibility with the vmstate dump. Bit 0 (0x0001) was + * previously used for CPU_INTERRUPT_EXIT, and is cleared when loading + * the vmstate dump. + */ +enum CPUInterruptFlags { + CPU_INTERRUPT_HARD = 0x0002, + CPU_INTERRUPT_EXITTB = 0x0004, + CPU_INTERRUPT_HALT = 0x0020, + CPU_INTERRUPT_DEBUG = 0x0080, + +#if defined(CONFIG_SOFTMMU) || defined(CONFIG_USER_ONLY) + /* Several target-specific external hardware interrupts. + * Each target/cpu.h should define proper names based on them. + */ + CPU_INTERRUPT_TGT_EXT_0 = 0x0008, + CPU_INTERRUPT_TGT_EXT_1 = 0x0010, + CPU_INTERRUPT_TGT_EXT_2 = 0x0040, + CPU_INTERRUPT_TGT_EXT_3 = 0x0200, + CPU_INTERRUPT_TGT_EXT_4 = 0x1000, + + /* Several target-specific internal interrupts. These differ from the + * preceding target-specific interrupts in that they are intended to + * originate from within the cpu itself, typically in response to some + * instruction being executed. These, therefore, are not masked while + * single-stepping within the debugger. + */ + CPU_INTERRUPT_TGT_INT_0 = 0x0100, + CPU_INTERRUPT_TGT_INT_1 = 0x0400, + CPU_INTERRUPT_TGT_INT_2 = 0x0800, + CPU_INTERRUPT_TGT_INT_3 = 0x2000, + + /* First unused bit: 0x4000. */ + + CPU_INTERRUPT_SSTEP_MASK = CPU_INTERRUPT_HARD | + CPU_INTERRUPT_TGT_EXT_0 | + CPU_INTERRUPT_TGT_EXT_1 | + CPU_INTERRUPT_TGT_EXT_2 | + CPU_INTERRUPT_TGT_EXT_3 | + CPU_INTERRUPT_TGT_EXT_4, +#endif +}; + #ifndef CONFIG_USER_ONLY typedef void (*CPUInterruptHandler)(CPUState *, int);