From patchwork Fri Jan 4 21:29:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Herv=C3=A9_Poussineau?= X-Patchwork-Id: 209567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D62FB2C008E for ; Sat, 5 Jan 2013 09:49:13 +1100 (EST) Received: from localhost ([::1]:56912 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TrG4e-0002pv-3N for incoming@patchwork.ozlabs.org; Fri, 04 Jan 2013 17:49:12 -0500 Received: from eggs.gnu.org ([208.118.235.92]:55705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TrEqE-0008U4-33 for qemu-devel@nongnu.org; Fri, 04 Jan 2013 16:30:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TrEqC-0005Ve-Pm for qemu-devel@nongnu.org; Fri, 04 Jan 2013 16:30:13 -0500 Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]:34201) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TrEqC-0005VP-7r for qemu-devel@nongnu.org; Fri, 04 Jan 2013 16:30:12 -0500 Received: from localhost.localdomain (unknown [82.227.227.196]) by smtp1-g21.free.fr (Postfix) with ESMTP id CCEE294004D; Fri, 4 Jan 2013 22:30:06 +0100 (CET) From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= To: qemu-devel@nongnu.org Date: Fri, 4 Jan 2013 22:29:41 +0100 Message-Id: <1357334986-13941-7-git-send-email-hpoussin@reactos.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1357334986-13941-1-git-send-email-hpoussin@reactos.org> References: <1357334986-13941-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a01:e0c:1:1599::10 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [Qemu-devel] [PATCH 06/10] acpi-piix4: do not use old_portio-style callbacks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Hervé Poussineau --- hw/acpi_piix4.c | 91 ++++++++++++++++++++++++------------------------------- 1 file changed, 40 insertions(+), 51 deletions(-) diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 06a8aca..63b41db 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -531,68 +531,57 @@ static const MemoryRegionOps piix4_gpe_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static uint32_t pci_up_read(void *opaque, uint32_t addr) +static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size) { PIIX4PMState *s = opaque; - uint32_t val; - - /* Manufacture an "up" value to cause a device check on any hotplug - * slot with a device. Extra device checks are harmless. */ - val = s->pci0_slot_device_present & s->pci0_hotplug_enable; - - PIIX4_DPRINTF("pci_up_read %x\n", val); - return val; -} - -static uint32_t pci_down_read(void *opaque, uint32_t addr) -{ - PIIX4PMState *s = opaque; - uint32_t val = s->pci0_status.down; + uint32_t val = 0; + + switch (addr) { + case PCI_UP_BASE - PCI_HOTPLUG_ADDR: + /* Manufacture an "up" value to cause a device check on any hotplug + * slot with a device. Extra device checks are harmless. */ + val = s->pci0_slot_device_present & s->pci0_hotplug_enable; + PIIX4_DPRINTF("pci_up_read %x\n", val); + break; + case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR: + val = s->pci0_status.down; + PIIX4_DPRINTF("pci_down_read %x\n", val); + break; + case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: + /* No feature defined yet */ + PIIX4_DPRINTF("pci_features_read %x\n", val); + break; + case PCI_RMV_BASE - PCI_HOTPLUG_ADDR: + val = s->pci0_hotplug_enable; + break; + default: + break; + } - PIIX4_DPRINTF("pci_down_read %x\n", val); return val; } -static uint32_t pci_features_read(void *opaque, uint32_t addr) -{ - /* No feature defined yet */ - PIIX4_DPRINTF("pci_features_read %x\n", 0); - return 0; -} - -static void pciej_write(void *opaque, uint32_t addr, uint32_t val) -{ - acpi_piix_eject_slot(opaque, val); - - PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val); -} - -static uint32_t pcirmv_read(void *opaque, uint32_t addr) +static void pci_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) { - PIIX4PMState *s = opaque; - - return s->pci0_hotplug_enable; + switch (addr) { + case PCI_EJ_BASE - PCI_HOTPLUG_ADDR: + acpi_piix_eject_slot(opaque, (uint32_t)data); + PIIX4_DPRINTF("pciej write %x <== % " PRIu64 "\n", addr, data); + break; + default: + break; + } } static const MemoryRegionOps piix4_pci_ops = { - .old_portio = (MemoryRegionPortio[]) { - { - .offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, - .read = pci_up_read, - },{ - .offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, - .read = pci_down_read, - },{ - .offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, - .read = pci_features_read, - .write = pciej_write, - },{ - .offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4, - .read = pcirmv_read, - }, - PORTIO_END_OF_LIST() + .read = pci_read, + .write = pci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, }, - .endianness = DEVICE_LITTLE_ENDIAN, }; static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,