From patchwork Tue Oct 9 20:27:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190427 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4C5E42C00A9 for ; Wed, 10 Oct 2012 07:28:09 +1100 (EST) Received: from localhost ([::1]:42657 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgPO-0007Nv-0M for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:28:06 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP4-0007Mh-8k for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgP1-0004Nx-Rp for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:46 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45230) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP1-0004NB-If for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:43 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgP0-0006xm-3S; Tue, 09 Oct 2012 22:27:42 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgOy-0005fs-7a; Tue, 09 Oct 2012 22:27:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:27:27 +0200 Message-Id: <1349814458-21739-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> References: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 03/14] target-mips: fix FPU exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For each FPU instruction that can trigger an FPU exception, it is needed to reset the softfloat status before and call update_fcr31() after. Remove the manual NaN assignment in case of float to float operation, as softfloat is already taking care of that. However for float to int operation, the value has to be changed to the MIPS one. In the cvtpw_ps case, the two registers have to be handled separately to guarantee a correct final value in both registers. Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 9d6d54a..bd3c37c 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2444,12 +2444,18 @@ static inline void update_fcr31(CPUMIPSState *env) /* unary operations, modifying fp status */ uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) { - return float64_sqrt(fdt0, &env->active_fpu.fp_status); + set_float_exception_flags(0, &env->active_fpu.fp_status); + fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); + update_fcr31(env); + return fdt0; } uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) { - return float32_sqrt(fst0, &env->active_fpu.fp_status); + set_float_exception_flags(0, &env->active_fpu.fp_status); + fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); + update_fcr31(env); + return fst0; } uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) @@ -2522,15 +2528,25 @@ uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; uint32_t wth2; + int excp, excph; set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); - wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + excp = get_float_exception_flags(&env->active_fpu.fp_status); + if (excp & (float_flag_overflow | float_flag_invalid)) { wt2 = FLOAT_SNAN32; + } + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); + excph = get_float_exception_flags(&env->active_fpu.fp_status); + if (excph & (float_flag_overflow | float_flag_invalid)) { wth2 = FLOAT_SNAN32; } + + set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); + update_fcr31(env); + return ((uint64_t)wth2 << 32) | wt2; } @@ -2970,8 +2986,6 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ update_fcr31(env); \ - if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ - dt2 = FLOAT_QNAN64; \ return dt2; \ } \ \ @@ -2983,8 +2997,6 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ update_fcr31(env); \ - if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ - wt2 = FLOAT_QNAN32; \ return wt2; \ } \ \ @@ -3003,10 +3015,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ update_fcr31(env); \ - if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ - wt2 = FLOAT_QNAN32; \ - wth2 = FLOAT_QNAN32; \ - } \ return ((uint64_t)wth2 << 32) | wt2; \ }