From patchwork Tue Oct 9 18:19:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 190401 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F10CC2C00B9 for ; Wed, 10 Oct 2012 05:27:19 +1100 (EST) Received: from localhost ([::1]:47676 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLeWU-00068m-0k for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 14:27:18 -0400 Received: from eggs.gnu.org ([208.118.235.92]:34597) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLeW8-0005mR-Ag for qemu-devel@nongnu.org; Tue, 09 Oct 2012 14:27:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLeW6-00035J-J8 for qemu-devel@nongnu.org; Tue, 09 Oct 2012 14:26:56 -0400 Received: from va3ehsobe006.messaging.microsoft.com ([216.32.180.16]:3691 helo=va3outboundpool.messaging.microsoft.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLeW6-00034p-EN; Tue, 09 Oct 2012 14:26:54 -0400 Received: from mail223-va3-R.bigfish.com (10.7.14.250) by VA3EHSOBE001.bigfish.com (10.7.40.21) with Microsoft SMTP Server id 14.1.225.23; Tue, 9 Oct 2012 18:26:54 +0000 Received: from mail223-va3 (localhost [127.0.0.1]) by mail223-va3-R.bigfish.com (Postfix) with ESMTP id AB000B0015D; Tue, 9 Oct 2012 18:26:53 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(zz168aJzz1202h1d1ah1d2ah1082kzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1155h) Received: from mail223-va3 (localhost.localdomain [127.0.0.1]) by mail223-va3 (MessageSwitch) id 1349807212110837_3210; Tue, 9 Oct 2012 18:26:52 +0000 (UTC) Received: from VA3EHSMHS011.bigfish.com (unknown [10.7.14.251]) by mail223-va3.bigfish.com (Postfix) with ESMTP id 18C6F180069; Tue, 9 Oct 2012 18:26:52 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS011.bigfish.com (10.7.99.21) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 9 Oct 2012 18:26:50 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.309.3; Tue, 9 Oct 2012 18:26:49 +0000 Received: from freescale.com ([10.232.15.72]) by az84smr01.freescale.net (8.14.3/8.14.0) with SMTP id q99IQjPC023647; Tue, 9 Oct 2012 11:26:46 -0700 Received: by freescale.com (sSMTP sendmail emulation); Tue, 09 Oct 2012 23:49:23 +0530 From: Bharat Bhushan To: , , , Date: Tue, 9 Oct 2012 23:49:10 +0530 Message-ID: <1349806750-17652-3-git-send-email-Bharat.Bhushan@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349806750-17652-1-git-send-email-Bharat.Bhushan@freescale.com> References: <1349806750-17652-1-git-send-email-Bharat.Bhushan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows XP/2000 (RFC1323+, w+, tstamp-) X-Received-From: 216.32.180.16 Cc: Bharat Bhushan Subject: [Qemu-devel] [PATCH 2/2 v2] Adding BAR0 for e500 PCI controller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root comaplex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with a address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: Bharat Bhushan Reviewed-by: Andreas Färber --- hw/ppc/e500-ccsr.h | 17 +++++++++++++++++ hw/ppc/e500.c | 39 ++++++++++++++++++++++++++++++++++++++- hw/ppce500_pci.c | 30 +++++++++++++++++++++++++++++- 3 files changed, 84 insertions(+), 2 deletions(-) create mode 100644 hw/ppc/e500-ccsr.h diff --git a/hw/ppc/e500-ccsr.h b/hw/ppc/e500-ccsr.h new file mode 100644 index 0000000..f20f51b --- /dev/null +++ b/hw/ppc/e500-ccsr.h @@ -0,0 +1,17 @@ +#ifndef E500_CCSR_H +#define E500_CCSR_H + +#include "../sysbus.h" + +typedef struct PPCE500CCSRState { + /*< private >*/ + SysBusDevice parent; + /*< public >*/ + + MemoryRegion ccsr_space; +} PPCE500CCSRState; + +#define TYPE_CCSR "e500-ccsr" +#define CCSR(obj) OBJECT_CHECK(PPCE500CCSRState, (obj), TYPE_CCSR) + +#endif /* E500_CCSR_H */ diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 187def2..d0433c2 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -17,6 +17,7 @@ #include "config.h" #include "qemu-common.h" #include "e500.h" +#include "e500-ccsr.h" #include "net.h" #include "hw/hw.h" #include "hw/pc.h" @@ -425,6 +426,7 @@ void ppce500_init(PPCE500Params *params) CPUPPCState *firstenv = NULL; MemoryRegion *ccsr; SysBusDevice *s; + PPCE500CCSRState *pci_ccsr; /* Setup CPUs */ if (params->cpu_model == NULL) { @@ -482,7 +484,12 @@ void ppce500_init(PPCE500Params *params) memory_region_add_subregion(address_space_mem, 0, ram); ccsr = g_malloc0(sizeof(MemoryRegion)); - memory_region_init(ccsr, "e500-ccsr", MPC8544_CCSRBAR_SIZE); + dev = qdev_create(NULL, "e500-ccsr"); + object_property_add_child(qdev_get_machine(), "e500-ccsr", + OBJECT(dev), NULL); + qdev_init_nofail(dev); + pci_ccsr = CCSR(dev); + ccsr = &pci_ccsr->ccsr_space; memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, ccsr); /* MPIC */ @@ -596,3 +603,33 @@ void ppce500_init(PPCE500Params *params) kvmppc_init(); } } + +static int e500_ccsr_initfn(SysBusDevice *dev) +{ + PPCE500CCSRState *pci_ccsr; + + pci_ccsr = CCSR(dev); + memory_region_init(&pci_ccsr->ccsr_space, "e500-ccsr", + MPC8544_CCSRBAR_SIZE); + return 0; +} + +static void e500_ccsr_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + k->init = e500_ccsr_initfn; +} + +static const TypeInfo e500_ccsr_info = { + .name = TYPE_CCSR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PPCE500CCSRState), + .class_init = e500_ccsr_class_init, +}; + +static void e500_register_types(void) +{ + type_register_static(&e500_ccsr_info); +} + +type_init(e500_register_types) diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 92b1dc0..58dbc1a 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -15,6 +15,7 @@ */ #include "hw.h" +#include "hw/ppc/e500-ccsr.h" #include "pci.h" #include "pci_host.h" #include "bswap.h" @@ -89,6 +90,19 @@ struct PPCE500PCIState { MemoryRegion iomem; }; +#define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" +#define PPC_E500_PCI_BRIDGE(obj) \ + OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) + +struct PPCE500PCIBridgeState { + /*< private >*/ + PCIDevice parent; + /*< public >*/ + + MemoryRegion bar0; +}; + +typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; typedef struct PPCE500PCIState PPCE500PCIState; static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr, @@ -307,6 +321,19 @@ static const VMStateDescription vmstate_ppce500_pci = { #include "exec-memory.h" +static int e500_pcihost_bridge_initfn(PCIDevice *d) +{ + PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); + PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), + "/e500-ccsr")); + + b->bar0 = ccsr->ccsr_space; + memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space, + 0, int128_get64(ccsr->ccsr_space.size)); + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); + return 0; +} + static int e500_pcihost_initfn(SysBusDevice *dev) { PCIHostState *h; @@ -350,6 +377,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + k->init = e500_pcihost_bridge_initfn; k->vendor_id = PCI_VENDOR_ID_FREESCALE; k->device_id = PCI_DEVICE_ID_MPC8533E; k->class_id = PCI_CLASS_PROCESSOR_POWERPC; @@ -359,7 +387,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data) static const TypeInfo e500_host_bridge_info = { .name = "e500-host-bridge", .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PCIDevice), + .instance_size = sizeof(PPCE500PCIBridgeState), .class_init = e500_host_bridge_class_init, };