From patchwork Fri Oct 5 00:08:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 189385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3A4862C0083 for ; Fri, 5 Oct 2012 10:53:34 +1000 (EST) Received: from localhost ([::1]:51788 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvUI-0004Ib-EJ for incoming@patchwork.ozlabs.org; Thu, 04 Oct 2012 20:09:54 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37293) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvTl-0002si-LN for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:09:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJvTk-0001uA-E0 for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:09:21 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:42758) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvTk-0001gF-6n for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:09:20 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so1027227pad.4 for ; Thu, 04 Oct 2012 17:09:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=i/iLR3M4O2XUftoRKieE3UMvAOd14t6uCXj1oUvaDUQ=; b=ivrnX9r/js3GpvaI8g22WVtBy3ntduJZrB+rW+NtfgTCxVYLuzyFpY+34s1txkY+30 8jUg/oXWEj7SuXr7i7gYa/ZlssopK0axfjSq5BEf2SNBnDGTjTo/zPD6nFbcwe9fso45 U9k4kuMImlHQI0yyXHkOI0GpraTnaoevJUgri3/ePX6bhBkgsoH3bcMSTikAkGdd9vPj G4rPb2rDDjyODVM7Ty1MMY5IOOIGVCdX8FvsRCtWiVy0iRGuSNLrM6zTfRdhiCwci0cD sE5jEujOuD48y8ATO/SByNCaFz+q8c0UoQe91pj+GHTqs5TiDp0zf2WNzhJ7XgvHiAmx XpmQ== Received: by 10.66.72.132 with SMTP id d4mr17105601pav.61.1349395759912; Thu, 04 Oct 2012 17:09:19 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id bs6sm5006618pab.30.2012.10.04.17.09.17 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 04 Oct 2012 17:09:19 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, blauwirbel@gmail.com, aliguori@us.ibm.com Date: Fri, 5 Oct 2012 10:08:49 +1000 Message-Id: <1349395739-26502-5-git-send-email-peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349395739-26502-1-git-send-email-peter.crosthwaite@xilinx.com> References: <1349395739-26502-1-git-send-email-peter.crosthwaite@xilinx.com> X-Gm-Message-State: ALoCoQkREKx1u31I6rElKG9Pplf3udVVSxS02W6KJPwABCjIlwod4wuwE7NMoKfMfulE3BAtf983 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: peter.crosthwaite@petalogix.com Subject: [Qemu-devel] [PATCH 04/14] qdev: allow multiple qdev_init_gpio_in() calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Allow multiple qdev_init_gpio_in() calls for the one device. The first call will define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled with different handlers. Needed when two levels of the QOM class heirachy both define GPIO functionality, as a single GPIO handler with an index selecter is not possible. Signed-off-by: Peter A. G. Crosthwaite Reviewed-by: Peter Maydell --- hw/irq.c | 27 ++++++++++++++++++++------- hw/irq.h | 11 ++++++++++- hw/qdev.c | 6 +++--- 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/irq.c b/hw/irq.c index d413a0b..f4e2a78 100644 --- a/hw/irq.c +++ b/hw/irq.c @@ -38,24 +38,37 @@ void qemu_set_irq(qemu_irq irq, int level) irq->handler(irq->opaque, irq->n, level); } -qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) +qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, + void *opaque, int n) { qemu_irq *s; struct IRQState *p; int i; - s = (qemu_irq *)g_malloc0(sizeof(qemu_irq) * n); - p = (struct IRQState *)g_malloc0(sizeof(struct IRQState) * n); - for (i = 0; i < n; i++) { - p->handler = handler; - p->opaque = opaque; - p->n = i; + if (!old) { + n_old = 0; + } + s = old ? g_renew(qemu_irq, old, n + n_old) : g_new(qemu_irq, n); + p = old ? g_renew(struct IRQState, s[0], n + n_old) : + g_new(struct IRQState, n); + for (i = 0; i < n + n_old; i++) { + if (i >= n_old) { + p->handler = handler; + p->opaque = opaque; + p->n = i; + } s[i] = p; p++; } return s; } +qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) +{ + return qemu_extend_irqs(NULL, 0, handler, opaque, n); +} + + void qemu_free_irqs(qemu_irq *s) { g_free(s[0]); diff --git a/hw/irq.h b/hw/irq.h index 56c55f0..e640c10 100644 --- a/hw/irq.h +++ b/hw/irq.h @@ -23,8 +23,17 @@ static inline void qemu_irq_pulse(qemu_irq irq) qemu_set_irq(irq, 0); } -/* Returns an array of N IRQs. */ +/* Returns an array of N IRQs. Each IRQ is assigned the argument handler and + * opaque data. + */ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n); + +/* Extends an Array of IRQs. Old IRQs have their handlers and opaque data + * preserved. New IRQs are assigned the argument handler and opaque data. + */ +qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler, + void *opaque, int n); + void qemu_free_irqs(qemu_irq *s); /* Returns a new IRQ with opposite polarity. */ diff --git a/hw/qdev.c b/hw/qdev.c index b5a52ac..eea9eae 100644 --- a/hw/qdev.c +++ b/hw/qdev.c @@ -291,9 +291,9 @@ BusState *qdev_get_parent_bus(DeviceState *dev) void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n) { - assert(dev->num_gpio_in == 0); - dev->num_gpio_in = n; - dev->gpio_in = qemu_allocate_irqs(handler, dev, n); + dev->gpio_in = qemu_extend_irqs(dev->gpio_in, dev->num_gpio_in, handler, + dev, n); + dev->num_gpio_in += n; } void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n)