From patchwork Thu Sep 20 22:59:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 185520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BEA962C007B for ; Fri, 21 Sep 2012 09:01:25 +1000 (EST) Received: from localhost ([::1]:36439 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEpkJ-0002Dh-T6 for incoming@patchwork.ozlabs.org; Thu, 20 Sep 2012 19:01:23 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56615) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEpk0-0001qG-Qb for qemu-devel@nongnu.org; Thu, 20 Sep 2012 19:01:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TEpjw-0005dd-DW for qemu-devel@nongnu.org; Thu, 20 Sep 2012 19:01:04 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:34996) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEpjw-0005dB-68; Thu, 20 Sep 2012 19:01:00 -0400 Received: by mail-lb0-f173.google.com with SMTP id gm13so3009751lbb.4 for ; Thu, 20 Sep 2012 16:00:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=D2lJXkmYZNtmlipT0yCz47nna2w+5k6jvDbuVQhRaNc=; b=aDZxtYpeQ7rDpmh5cCIqw2/N5HQ65roI8RkhNrv2lG+EMIO2SBJS0eNa6LY+SGpomk mEjH4POy1lKJcQnCQYtliAWc7fTjxksN9EOE67uo/mcEBwpQtEe3t6qcL2CCAKGrbAin YHjxNZjGpBDVY/6FJFJ9CaJLTxf51otcDLKNc4hGNS8gjm+ENxQ7sXiuMQ57wfItaUxz Mz1RhlJKcBE6rSsxJQh7Tkna4AjWp7yVaFhhrEffABhNCwtnZ/4F8DV+0KORnckL/OcA LwkDHkSvUnvX+c2vRsC2CEF2gCCIuSlw+q4vM/OjXjSeb7wySgAg4imGhJi9t7cjynDq yZRQ== Received: by 10.112.85.193 with SMTP id j1mr1080334lbz.128.1348182059347; Thu, 20 Sep 2012 16:00:59 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id gt19sm1781060lab.8.2012.09.20.16.00.57 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 20 Sep 2012 16:00:58 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 02:59:49 +0400 Message-Id: <1348181990-23415-2-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1348181990-23415-1-git-send-email-jcmvbkbc@gmail.com> References: <1348181990-23415-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.217.173 Cc: Peter Maydell , qemu-stable , Max Filippov , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 1/2] target-xtensa: fix extui shift amount X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org extui opcode only uses lowermost op1 bit for sa4. Reported-by: malc Signed-off-by: Max Filippov Cc: qemu-stable --- target-xtensa/translate.c | 24 +++++++++++++++++++++--- 1 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1900bd5..7a1c528 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1778,12 +1778,30 @@ static void disas_xtensa_insn(DisasContext *dc) case 5: gen_window_check2(dc, RRR_R, RRR_T); { - int shiftimm = RRR_S | (OP1 << 4); + int shiftimm = RRR_S | ((OP1 & 1) << 4); int maskimm = (1 << (OP2 + 1)) - 1; TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); - tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); + + if (shiftimm) { + tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm); + } else { + tcg_gen_mov_i32(tmp, cpu_R[RRR_T]); + } + + switch (maskimm) { + case 0xff: + tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp); + break; + + case 0xffff: + tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp); + break; + + default: + tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm); + break; + } tcg_temp_free(tmp); } break;