From patchwork Fri Jul 6 15:49:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maksim E. Kozlov" X-Patchwork-Id: 169486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D526F2C01EA for ; Sat, 7 Jul 2012 01:50:02 +1000 (EST) Received: from localhost ([::1]:40954 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SnAnA-0003Ue-OY for incoming@patchwork.ozlabs.org; Fri, 06 Jul 2012 11:50:00 -0400 Received: from eggs.gnu.org ([208.118.235.92]:53577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SnAmw-0003NF-Gl for qemu-devel@nongnu.org; Fri, 06 Jul 2012 11:49:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SnAms-0001Ip-B3 for qemu-devel@nongnu.org; Fri, 06 Jul 2012 11:49:46 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:47206) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SnAms-0001H9-5U for qemu-devel@nongnu.org; Fri, 06 Jul 2012 11:49:42 -0400 Received: from eusync2.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6Q00GFNXBIN350@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Fri, 06 Jul 2012 16:50:06 +0100 (BST) Received: from felix.rnd.samsung.ru ([106.109.9.187]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0M6Q0045TXAGJ180@eusync2.samsung.com> for qemu-devel@nongnu.org; Fri, 06 Jul 2012 16:49:37 +0100 (BST) From: Maksim Kozlov To: qemu-devel@nongnu.org Date: Fri, 06 Jul 2012 19:49:26 +0400 Message-id: <1341589767-9895-4-git-send-email-m.kozlov@samsung.com> X-Mailer: git-send-email 1.7.5.4 In-reply-to: <1341589767-9895-1-git-send-email-m.kozlov@samsung.com> References: <1341589767-9895-1-git-send-email-m.kozlov@samsung.com> X-TM-AS-MML: No X-detected-operating-system: by eggs.gnu.org: Solaris 10 (1203?) X-Received-From: 210.118.77.12 Cc: peter.maydell@linaro.org, kyungmin.park@samsung.com, Maksim Kozlov Subject: [Qemu-devel] [PATCH 3/4] ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch just introduces exynos4210_pmu_get_register_index function to get index of the register's value in the array on its offset. And functions _read and _write were modified accordingly. Signed-off-by: Maksim Kozlov Reviewed-by: Peter Maydell --- hw/exynos4210_pmu.c | 56 ++++++++++++++++++++++++++++++++------------------ 1 files changed, 36 insertions(+), 20 deletions(-) diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c index 26a726f..7f09c79 100644 --- a/hw/exynos4210_pmu.c +++ b/hw/exynos4210_pmu.c @@ -401,48 +401,64 @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = { #define PMU_NUM_OF_REGISTERS \ (sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg)) +#define PMU_UNKNOWN_OFFSET 0xFFFFFFFF + typedef struct Exynos4210PmuState { SysBusDevice busdev; MemoryRegion iomem; uint32_t reg[PMU_NUM_OF_REGISTERS]; } Exynos4210PmuState; -static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset, - unsigned size) +static uint32_t exynos4210_pmu_get_register_index(Exynos4210PmuState *s, + uint32_t offset) { - Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; - unsigned i; const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs; + uint32_t i; for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { if (reg_p->offset == offset) { - PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name, - (uint32_t)offset, s->reg[i]); - return s->reg[i]; + return i; } reg_p++; } - PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset); - return 0; + + return PMU_UNKNOWN_OFFSET; +} + +static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; + uint32_t index = exynos4210_pmu_get_register_index(s, offset); + + if (index == PMU_UNKNOWN_OFFSET) { + PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", + (uint32_t)offset); + return 0; + } + + PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", + exynos4210_pmu_regs[index].name, (uint32_t)offset, s->reg[index]); + + return s->reg[index]; } static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, uint64_t val, unsigned size) { Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; - unsigned i; - const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs; + uint32_t index = exynos4210_pmu_get_register_index(s, offset); - for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { - if (reg_p->offset == offset) { - PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name, - (uint32_t)offset, (uint32_t)val); - s->reg[i] = val; - return; - } - reg_p++; + if (index == PMU_UNKNOWN_OFFSET) { + PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", + (uint32_t)offset); + return; } - PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset); + + PRINT_DEBUG_EXTEND("%s [0x%04x] <- 0x%04x\n", + exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val); + + s->reg[index] = val; } static const MemoryRegionOps exynos4210_pmu_ops = {