From patchwork Thu May 10 00:14:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 158148 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 6E1F2B6F6E for ; Thu, 10 May 2012 12:52:24 +1000 (EST) Received: from localhost ([::1]:48497 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH4K-0004Py-Ha for incoming@patchwork.ozlabs.org; Wed, 09 May 2012 20:17:20 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH2W-0001gY-7f for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SSH2T-0005hy-SU for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:27 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35629 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SSH2T-0005gu-I4 for qemu-devel@nongnu.org; Wed, 09 May 2012 20:15:25 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 7B3EF978B8 for ; Thu, 10 May 2012 02:15:24 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Thu, 10 May 2012 02:14:37 +0200 Message-Id: <1336608892-30501-60-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1336608892-30501-1-git-send-email-afaerber@suse.de> References: <1336608892-30501-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH next v2 59/74] microblaze_boot: Pass MicroBlazeCPU to microblaze_load_kernel() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Allows us to use cpu_reset() in place of cpu_state_reset() in main_cpu_reset(). Also pass it through to its reset callbacks, while at it. Signed-off-by: Andreas Färber --- hw/microblaze_boot.c | 16 ++++++++-------- hw/microblaze_boot.h | 4 ++-- hw/petalogix_ml605_mmu.c | 6 ++++-- hw/petalogix_s3adsp1800_mmu.c | 6 ++++-- 4 files changed, 18 insertions(+), 14 deletions(-) diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c index b4fbb10..1030e9c 100644 --- a/hw/microblaze_boot.c +++ b/hw/microblaze_boot.c @@ -35,7 +35,7 @@ static struct { - void (*machine_cpu_reset)(CPUMBState *); + void (*machine_cpu_reset)(MicroBlazeCPU *); uint32_t bootstrap_pc; uint32_t cmdline; uint32_t fdt; @@ -43,14 +43,15 @@ static struct static void main_cpu_reset(void *opaque) { - CPUMBState *env = opaque; + MicroBlazeCPU *cpu = opaque; + CPUMBState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->regs[5] = boot_info.cmdline; env->regs[7] = boot_info.fdt; env->sregs[SR_PC] = boot_info.bootstrap_pc; if (boot_info.machine_cpu_reset) { - boot_info.machine_cpu_reset(env); + boot_info.machine_cpu_reset(cpu); } } @@ -99,11 +100,10 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x30000000LL; } -void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUMBState *)) + void (*machine_cpu_reset)(MicroBlazeCPU *)) { - QemuOpts *machine_opts; const char *kernel_filename = NULL; const char *kernel_cmdline = NULL; @@ -122,7 +122,7 @@ void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, } boot_info.machine_cpu_reset = machine_cpu_reset; - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); if (kernel_filename) { int kernel_size; diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h index bf9d136..c9a3064 100644 --- a/hw/microblaze_boot.h +++ b/hw/microblaze_boot.h @@ -3,8 +3,8 @@ #include "hw.h" -void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUMBState *)); + void (*machine_cpu_reset)(MicroBlazeCPU *)); #endif /* __MICROBLAZE_BOOT __ */ diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index 6819241..bff63e3 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -54,8 +54,10 @@ #define AXIENET_BASEADDR 0x82780000 #define AXIDMA_BASEADDR 0x84600000 -static void machine_cpu_reset(CPUMBState *env) +static void machine_cpu_reset(MicroBlazeCPU *cpu) { + CPUMBState *env = &cpu->env; + env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; @@ -133,7 +135,7 @@ petalogix_ml605_init(ram_addr_t ram_size, irq[1], irq[0], 100 * 1000000); } - microblaze_load_kernel(env, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, + microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset); } diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 7ff3cd5..f41c559 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -49,8 +49,10 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 -static void machine_cpu_reset(CPUMBState *env) +static void machine_cpu_reset(MicroBlazeCPU *cpu) { + CPUMBState *env = &cpu->env; + env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */ } @@ -107,7 +109,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); - microblaze_load_kernel(env, ddr_base, ram_size, + microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset); }