From patchwork Sun Apr 15 18:38:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 152679 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9F0ABB6FFD for ; Mon, 16 Apr 2012 04:39:45 +1000 (EST) Received: from localhost ([::1]:42133 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJUMR-0008P8-D1 for incoming@patchwork.ozlabs.org; Sun, 15 Apr 2012 14:39:43 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJUM0-0007gD-27 for qemu-devel@nongnu.org; Sun, 15 Apr 2012 14:39:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SJULw-0002m1-Ee for qemu-devel@nongnu.org; Sun, 15 Apr 2012 14:39:15 -0400 Received: from cantor2.suse.de ([195.135.220.15]:35580 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SJULw-0002lY-8A; Sun, 15 Apr 2012 14:39:12 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id D71B68FFEB; Sun, 15 Apr 2012 20:39:10 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 15 Apr 2012 20:38:45 +0200 Message-Id: <1334515144-26485-2-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1334515144-26485-1-git-send-email-afaerber@suse.de> References: <1334515144-26485-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: blauwirbel@gmail.com, Mark Cave-Ayland , qemu-ppc@nongnu.org, agraf@suse.de, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH 01/20] PPC: Fix TLB invalidation bug within the PPC interrupt handler. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Mark Cave-Ayland Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR bits at the start of the interrupt handler, the logic towards the end of the handler to force a TLB flush if either one of these bits were set would never be triggered. This patch simply changes the IR/DR bit check in the TLB flush logic to use the original MSR value (albeit with some interrupt-specific bits cleared) so that the IR/DR bits are preserved at the point where the check takes place. Signed-off-by: Mark Cave-Ayland Acked-by: David Gibson Signed-off-by: Andreas Färber --- target-ppc/helper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index e13b749..f0ea1c3 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2960,7 +2960,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) if (asrr1 != -1) env->spr[asrr1] = env->spr[srr1]; /* If we disactivated any translation, flush TLBs */ - if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) + if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) tlb_flush(env, 1); if (msr_ile) {