From patchwork Wed Mar 14 16:01:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 146660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4971BB6F62 for ; Thu, 15 Mar 2012 03:02:15 +1100 (EST) Received: from localhost ([::1]:37145 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qeS-00046o-Ve for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 12:02:12 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qeF-00041I-OU for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:02:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7qe5-0002BF-E2 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:01:59 -0400 Received: from cantor2.suse.de ([195.135.220.15]:44468 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7qe5-0002Ah-58 for qemu-devel@nongnu.org; Wed, 14 Mar 2012 12:01:49 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 6D7F590072; Wed, 14 Mar 2012 17:01:44 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Wed, 14 Mar 2012 17:01:30 +0100 Message-Id: <1331740900-5637-3-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1331740900-5637-1-git-send-email-afaerber@suse.de> References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331740900-5637-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno Subject: [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Move them out of CPUSH4State so that they are not zero'ed on reset. Signed-off-by: Andreas Färber --- hw/sh7750.c | 5 +++-- target-sh4/cpu-qom.h | 3 +++ target-sh4/cpu.c | 3 ++- target-sh4/cpu.h | 3 --- target-sh4/translate.c | 3 ++- 5 files changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/sh7750.c b/hw/sh7750.c index e712928..c7e653c 100644 --- a/hw/sh7750.c +++ b/hw/sh7750.c @@ -77,10 +77,11 @@ typedef struct SH7750State { struct intc_desc intc; } SH7750State; -static inline int has_bcr3_and_bcr4(SH7750State * s) +static inline int has_bcr3_and_bcr4(SH7750State *s) { - return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4); + return sh_env_get_cpu(s->cpu)->features & SH_FEATURE_BCR3_AND_BCR4; } + /********************************************************************** I/O ports **********************************************************************/ diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index 1441328..c8cc63e 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -55,6 +55,7 @@ typedef struct SuperHCPUClass { /** * SuperHCPU: + * @features: CPU feature flags, see #sh_features. * @env: Legacy CPU state. * * A SuperH CPU. @@ -64,6 +65,8 @@ typedef struct SuperHCPU { CPUState parent_obj; /*< public >*/ + uint32_t features; + CPUSH4State env; } SuperHCPU; diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 68034b6..d1bd156 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -94,6 +94,8 @@ static void superh_cpu_initfn(Object *obj) SuperHCPUClass *klass = SUPERH_CPU_GET_CLASS(cpu); CPUSH4State *env = &cpu->env; + cpu->features = klass->features; + memset(env, 0, sizeof(CPUSH4State)); env->cpu_model_str = object_get_typename(obj); cpu_exec_init(env); @@ -102,7 +104,6 @@ static void superh_cpu_initfn(Object *obj) env->pvr = klass->pvr; env->prr = klass->prr; env->cvr = klass->cvr; - env->features = klass->features; env->movcal_backup_tail = &(env->movcal_backup); diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index ec5e6cf..ee8ba5e 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -157,9 +157,6 @@ typedef struct CPUSH4State { /* float point status register */ float_status fp_status; - /* The features that we should emulate. See sh_features above. */ - uint32_t features; - /* Those belong to the specific unit (SH7750) but are handled here */ uint32_t mmucr; /* MMU control register */ uint32_t pteh; /* page table entry high register */ diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 71434d0..d43cd8c 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1876,6 +1876,7 @@ static inline void gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, int search_pc) { + SuperHCPU *cpu = sh_env_get_cpu(env); DisasContext ctx; target_ulong pc_start; static uint16_t *gen_opc_end; @@ -1897,7 +1898,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, ctx.delayed_pc = -1; /* use delayed pc from env pointer */ ctx.tb = tb; ctx.singlestep_enabled = env->singlestep_enabled; - ctx.features = env->features; + ctx.features = cpu->features; ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA); ii = -1;