| Message ID | 1331346496-10736-3-git-send-email-afaerber@suse.de |
|---|---|
| State | New |
| Headers | show |
On 03/09/2012 08:27 PM, Andreas Färber wrote: > Frees the identifier cpu_reset for QOM CPUs (manual rename). > > Don't hide the parameter type behind explicit casts, use static > functions with strongly typed argument to indirect. > > Signed-off-by: Andreas Färber<afaerber@suse.de> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Regards, Anthony Liguori > --- > bsd-user/main.c | 2 +- > cpu-all.h | 2 +- > cpu-exec.c | 2 +- > darwin-user/main.c | 2 +- > hw/arm_boot.c | 2 +- > hw/armv7m.c | 2 +- > hw/cris-boot.c | 2 +- > hw/leon3.c | 2 +- > hw/lm32_boards.c | 2 +- > hw/microblaze_boot.c | 2 +- > hw/milkymist.c | 2 +- > hw/mips_fulong2e.c | 2 +- > hw/mips_jazz.c | 2 +- > hw/mips_malta.c | 2 +- > hw/mips_mipssim.c | 2 +- > hw/mips_r4k.c | 2 +- > hw/omap1.c | 2 +- > hw/omap2.c | 2 +- > hw/pc.c | 2 +- > hw/ppc440_bamboo.c | 2 +- > hw/ppc4xx_devs.c | 9 ++++++++- > hw/ppc_newworld.c | 9 ++++++++- > hw/ppc_oldworld.c | 9 ++++++++- > hw/ppc_prep.c | 9 ++++++++- > hw/ppce500_mpc8544ds.c | 4 ++-- > hw/pxa2xx.c | 2 +- > hw/r2d.c | 2 +- > hw/spapr.c | 9 ++++++++- > hw/sun4m.c | 4 ++-- > hw/sun4u.c | 2 +- > hw/virtex_ml507.c | 2 +- > hw/xtensa_lx60.c | 8 +++++--- > hw/xtensa_sim.c | 2 +- > linux-user/main.c | 2 +- > linux-user/syscall.c | 2 +- > target-arm/helper.c | 4 ++-- > target-cris/translate.c | 4 ++-- > target-i386/helper.c | 4 ++-- > target-lm32/helper.c | 4 ++-- > target-m68k/helper.c | 4 ++-- > target-microblaze/translate.c | 4 ++-- > target-mips/helper.c | 2 +- > target-mips/translate.c | 4 ++-- > target-ppc/helper.c | 2 +- > target-s390x/helper.c | 4 ++-- > target-sh4/translate.c | 4 ++-- > target-sparc/cpu_init.c | 2 +- > target-xtensa/helper.c | 2 +- > 48 files changed, 98 insertions(+), 61 deletions(-) > > diff --git a/bsd-user/main.c b/bsd-user/main.c > index cdb0d0a..c3af395 100644 > --- a/bsd-user/main.c > +++ b/bsd-user/main.c > @@ -917,7 +917,7 @@ int main(int argc, char **argv) > exit(1); > } > #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) > - cpu_reset(env); > + cpu_state_reset(env); > #endif > thread_env = env; > > diff --git a/cpu-all.h b/cpu-all.h > index 80e6d42..7586c0d 100644 > --- a/cpu-all.h > +++ b/cpu-all.h > @@ -433,7 +433,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask); > #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ > > void cpu_single_step(CPUState *env, int enabled); > -void cpu_reset(CPUState *s); > +void cpu_state_reset(CPUState *s); > int cpu_is_stopped(CPUState *env); > void run_on_cpu(CPUState *env, void (*func)(void *data), void *data); > > diff --git a/cpu-exec.c b/cpu-exec.c > index 3d28053..2bf1735 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -340,7 +340,7 @@ int cpu_exec(CPUState *env) > } > #elif defined(TARGET_PPC) > if ((interrupt_request& CPU_INTERRUPT_RESET)) { > - cpu_reset(env); > + cpu_state_reset(env); > } > if (interrupt_request& CPU_INTERRUPT_HARD) { > ppc_hw_interrupt(env); > diff --git a/darwin-user/main.c b/darwin-user/main.c > index e1519c7..13c1f05 100644 > --- a/darwin-user/main.c > +++ b/darwin-user/main.c > @@ -858,7 +858,7 @@ int main(int argc, char **argv) > /* NOTE: we need to init the CPU at this stage to get > qemu_host_page_size */ > env = cpu_init(cpu_model); > - cpu_reset(env); > + cpu_state_reset(env); > > printf("Starting %s with qemu\n----------------\n", filename); > > diff --git a/hw/arm_boot.c b/hw/arm_boot.c > index fc66910..23b3f0a 100644 > --- a/hw/arm_boot.c > +++ b/hw/arm_boot.c > @@ -277,7 +277,7 @@ static void do_cpu_reset(void *opaque) > CPUState *env = opaque; > const struct arm_boot_info *info = env->boot_info; > > - cpu_reset(env); > + cpu_state_reset(env); > if (info) { > if (!info->is_linux) { > /* Jump to the entry point. */ > diff --git a/hw/armv7m.c b/hw/armv7m.c > index 6b80579..9cf96f4 100644 > --- a/hw/armv7m.c > +++ b/hw/armv7m.c > @@ -149,7 +149,7 @@ static void armv7m_bitband_init(void) > > static void armv7m_reset(void *opaque) > { > - cpu_reset((CPUState *)opaque); > + cpu_state_reset((CPUState *)opaque); > } > > /* Init CPU and memory for a v7-M based board. > diff --git a/hw/cris-boot.c b/hw/cris-boot.c > index 37894f8..ade517d 100644 > --- a/hw/cris-boot.c > +++ b/hw/cris-boot.c > @@ -34,7 +34,7 @@ static void main_cpu_reset(void *opaque) > > li = env->load_info; > > - cpu_reset(env); > + cpu_state_reset(env); > > if (!li) { > /* nothing more to do. */ > diff --git a/hw/leon3.c b/hw/leon3.c > index 71d79a6..1dc5a02 100644 > --- a/hw/leon3.c > +++ b/hw/leon3.c > @@ -51,7 +51,7 @@ static void main_cpu_reset(void *opaque) > ResetData *s = (ResetData *)opaque; > CPUState *env = s->env; > > - cpu_reset(env); > + cpu_state_reset(env); > > env->halted = 0; > env->pc = s->entry; > diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c > index 3cdf120..51c8a0f 100644 > --- a/hw/lm32_boards.c > +++ b/hw/lm32_boards.c > @@ -56,7 +56,7 @@ static void main_cpu_reset(void *opaque) > ResetInfo *reset_info = opaque; > CPUState *env = reset_info->env; > > - cpu_reset(env); > + cpu_state_reset(env); > > /* init defaults */ > env->pc = (uint32_t)reset_info->bootstrap_pc; > diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c > index b2f96df..7ce04dc 100644 > --- a/hw/microblaze_boot.c > +++ b/hw/microblaze_boot.c > @@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > env->regs[5] = boot_info.cmdline; > env->regs[7] = boot_info.fdt; > env->sregs[SR_PC] = boot_info.bootstrap_pc; > diff --git a/hw/milkymist.c b/hw/milkymist.c > index eaef0c2..7ec6554 100644 > --- a/hw/milkymist.c > +++ b/hw/milkymist.c > @@ -61,7 +61,7 @@ static void main_cpu_reset(void *opaque) > ResetInfo *reset_info = opaque; > CPUState *env = reset_info->env; > > - cpu_reset(env); > + cpu_state_reset(env); > > /* init defaults */ > env->pc = reset_info->bootstrap_pc; > diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c > index e3ba9dd..2db8ba0 100644 > --- a/hw/mips_fulong2e.c > +++ b/hw/mips_fulong2e.c > @@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > /* TODO: 2E reset stuff */ > if (loaderparams.kernel_filename) { > env->CP0_Status&= ~((1<< CP0St_BEV) | (1<< CP0St_ERL)); > diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c > index 2b4678e..d5f1b34 100644 > --- a/hw/mips_jazz.c > +++ b/hw/mips_jazz.c > @@ -51,7 +51,7 @@ enum jazz_model_e > static void main_cpu_reset(void *opaque) > { > CPUState *env = opaque; > - cpu_reset(env); > + cpu_state_reset(env); > } > > static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) > diff --git a/hw/mips_malta.c b/hw/mips_malta.c > index b1563ed..887faea 100644 > --- a/hw/mips_malta.c > +++ b/hw/mips_malta.c > @@ -746,7 +746,7 @@ static void malta_mips_config(CPUState *env) > static void main_cpu_reset(void *opaque) > { > CPUState *env = opaque; > - cpu_reset(env); > + cpu_state_reset(env); > > /* The bootloader does not need to be rewritten as it is located in a > read only location. The kernel location and the arguments table > diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c > index 76c95b2..1fe4ac5 100644 > --- a/hw/mips_mipssim.c > +++ b/hw/mips_mipssim.c > @@ -107,7 +107,7 @@ static void main_cpu_reset(void *opaque) > ResetData *s = (ResetData *)opaque; > CPUState *env = s->env; > > - cpu_reset(env); > + cpu_state_reset(env); > env->active_tc.PC = s->vector& ~(target_ulong)1; > if (s->vector& 1) { > env->hflags |= MIPS_HFLAG_M16; > diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c > index 83401f0..96ad808 100644 > --- a/hw/mips_r4k.c > +++ b/hw/mips_r4k.c > @@ -145,7 +145,7 @@ static void main_cpu_reset(void *opaque) > ResetData *s = (ResetData *)opaque; > CPUState *env = s->env; > > - cpu_reset(env); > + cpu_state_reset(env); > env->active_tc.PC = s->vector; > } > > diff --git a/hw/omap1.c b/hw/omap1.c > index 1aa5f23..5317b9b 100644 > --- a/hw/omap1.c > +++ b/hw/omap1.c > @@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque) > omap_lpg_reset(mpu->led[0]); > omap_lpg_reset(mpu->led[1]); > omap_clkm_reset(mpu); > - cpu_reset(mpu->env); > + cpu_state_reset(mpu->env); > } > > static const struct omap_map_s { > diff --git a/hw/omap2.c b/hw/omap2.c > index a6851b0..157defb 100644 > --- a/hw/omap2.c > +++ b/hw/omap2.c > @@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque) > omap_mcspi_reset(mpu->mcspi[1]); > omap_i2c_reset(mpu->i2c[0]); > omap_i2c_reset(mpu->i2c[1]); > - cpu_reset(mpu->env); > + cpu_state_reset(mpu->env); > } > > static int omap2_validate_addr(struct omap_mpu_state_s *s, > diff --git a/hw/pc.c b/hw/pc.c > index bb9867b..aca4460 100644 > --- a/hw/pc.c > +++ b/hw/pc.c > @@ -928,7 +928,7 @@ static void pc_cpu_reset(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > env->halted = !cpu_is_bsp(env); > } > > diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c > index f86b168..835e36d 100644 > --- a/hw/ppc440_bamboo.c > +++ b/hw/ppc440_bamboo.c > @@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > env->gpr[1] = (16<<20) - 8; > env->gpr[3] = FDT_ADDR; > env->nip = entry; > diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c > index 26040ac..2311162 100644 > --- a/hw/ppc4xx_devs.c > +++ b/hw/ppc4xx_devs.c > @@ -38,6 +38,13 @@ > # define LOG_UIC(...) do { } while (0) > #endif > > +static void ppc4xx_reset(void *opaque) > +{ > + CPUState *env = opaque; > + > + cpu_state_reset(env); > +} > + > /*****************************************************************************/ > /* Generic PowerPC 4xx processor instantiation */ > CPUState *ppc4xx_init (const char *cpu_model, > @@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model, > tb_clk->opaque = env; > ppc_dcr_init(env, NULL, NULL); > /* Register qemu callbacks */ > - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); > + qemu_register_reset(ppc4xx_reset, env); > > return env; > } > diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c > index 506187b..fd8e21d 100644 > --- a/hw/ppc_newworld.c > +++ b/hw/ppc_newworld.c > @@ -122,6 +122,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) > return (addr + TARGET_PAGE_SIZE - 1)& TARGET_PAGE_MASK; > } > > +static void ppc_core99_reset(void *opaque) > +{ > + CPUState *env = opaque; > + > + cpu_state_reset(env); > +} > + > /* PowerPC Mac99 hardware initialisation */ > static void ppc_core99_init (ram_addr_t ram_size, > const char *boot_device, > @@ -167,7 +174,7 @@ static void ppc_core99_init (ram_addr_t ram_size, > } > /* Set time-base frequency to 100 Mhz */ > cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); > - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); > + qemu_register_reset(ppc_core99_reset, env); > } > > /* allocate RAM */ > diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c > index 9295a34..085b825 100644 > --- a/hw/ppc_oldworld.c > +++ b/hw/ppc_oldworld.c > @@ -66,6 +66,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) > return (addr + TARGET_PAGE_SIZE - 1)& TARGET_PAGE_MASK; > } > > +static void ppc_heathrow_reset(void *opaque) > +{ > + CPUState *env = opaque; > + > + cpu_state_reset(env); > +} > + > static void ppc_heathrow_init (ram_addr_t ram_size, > const char *boot_device, > const char *kernel_filename, > @@ -105,7 +112,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, > } > /* Set time-base frequency to 16.6 Mhz */ > cpu_ppc_tb_init(env, 16600000UL); > - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); > + qemu_register_reset(ppc_heathrow_reset, env); > } > > /* allocate RAM */ > diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c > index eb43fb5..c5f2542 100644 > --- a/hw/ppc_prep.c > +++ b/hw/ppc_prep.c > @@ -471,6 +471,13 @@ static void cpu_request_exit(void *opaque, int irq, int level) > } > } > > +static void ppc_prep_reset(void *opaque) > +{ > + CPUState *env = opaque; > + > + cpu_state_reset(env); > +} > + > /* PowerPC PREP hardware initialisation */ > static void ppc_prep_init (ram_addr_t ram_size, > const char *boot_device, > @@ -525,7 +532,7 @@ static void ppc_prep_init (ram_addr_t ram_size, > /* Set time-base frequency to 100 Mhz */ > cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); > } > - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); > + qemu_register_reset(ppc_prep_reset, env); > } > > /* allocate RAM */ > diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c > index d69f78c..752aed9 100644 > --- a/hw/ppce500_mpc8544ds.c > +++ b/hw/ppce500_mpc8544ds.c > @@ -198,7 +198,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > > /* Secondary CPU starts in halted state for now. Needs to change when > implementing non-kernel boot. */ > @@ -211,7 +211,7 @@ static void mpc8544ds_cpu_reset(void *opaque) > CPUState *env = opaque; > struct boot_info *bi = env->load_info; > > - cpu_reset(env); > + cpu_state_reset(env); > > /* Set initial guest state. */ > env->halted = 0; > diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c > index 1ab2701..f552877 100644 > --- a/hw/pxa2xx.c > +++ b/hw/pxa2xx.c > @@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level) > PXA2xxState *s = (PXA2xxState *) opaque; > > if (level&& (s->pm_regs[PCFR>> 2]& 0x10)) { /* GPR_EN */ > - cpu_reset(s->env); > + cpu_state_reset(s->env); > /* TODO: reset peripherals */ > } > } > diff --git a/hw/r2d.c b/hw/r2d.c > index c80f9e3..ae327a7 100644 > --- a/hw/r2d.c > +++ b/hw/r2d.c > @@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque) > ResetData *s = (ResetData *)opaque; > CPUState *env = s->env; > > - cpu_reset(env); > + cpu_state_reset(env); > env->pc = s->vector; > } > > diff --git a/hw/spapr.c b/hw/spapr.c > index dffb6a2..3f9d87c 100644 > --- a/hw/spapr.c > +++ b/hw/spapr.c > @@ -502,6 +502,13 @@ static void spapr_reset(void *opaque) > > } > > +static void spapr_cpu_reset(void *opaque) > +{ > + CPUState *env = opaque; > + > + cpu_state_reset(env); > +} > + > /* pSeries LPAR / sPAPR hardware init */ > static void ppc_spapr_init(ram_addr_t ram_size, > const char *boot_device, > @@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size, > } > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, TIMEBASE_FREQ); > - qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); > + qemu_register_reset(spapr_cpu_reset, env); > > env->hreset_vector = 0x60; > env->hreset_excp_prefix = 0; > diff --git a/hw/sun4m.c b/hw/sun4m.c > index 99fb219..4045740 100644 > --- a/hw/sun4m.c > +++ b/hw/sun4m.c > @@ -283,7 +283,7 @@ static void main_cpu_reset(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > env->halted = 0; > } > > @@ -291,7 +291,7 @@ static void secondary_cpu_reset(void *opaque) > { > CPUState *env = opaque; > > - cpu_reset(env); > + cpu_state_reset(env); > env->halted = 1; > } > > diff --git a/hw/sun4u.c b/hw/sun4u.c > index 423108f..8b043f2 100644 > --- a/hw/sun4u.c > +++ b/hw/sun4u.c > @@ -376,7 +376,7 @@ static void main_cpu_reset(void *opaque) > CPUState *env = s->env; > static unsigned int nr_resets; > > - cpu_reset(env); > + cpu_state_reset(env); > > cpu_timer_reset(env->tick); > cpu_timer_reset(env->stick); > diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c > index f8d2b1b..e672490 100644 > --- a/hw/virtex_ml507.c > +++ b/hw/virtex_ml507.c > @@ -109,7 +109,7 @@ static void main_cpu_reset(void *opaque) > CPUState *env = opaque; > struct boot_info *bi = env->load_info; > > - cpu_reset(env); > + cpu_state_reset(env); > /* Linux Kernel Parameters (passing device tree): > * r3: pointer to the fdt > * r4: 0 > diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c > index 26112c3..80ba4d7 100644 > --- a/hw/xtensa_lx60.c > +++ b/hw/xtensa_lx60.c > @@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) > return cpu_get_phys_page_debug(env, addr); > } > > -static void lx60_reset(void *env) > +static void lx60_reset(void *opaque) > { > - cpu_reset(env); > + CPUState *env = opaque; > + > + cpu_state_reset(env); > } > > static void lx_init(const LxBoardDesc *board, > @@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board, > /* Need MMU initialized prior to ELF loading, > * so that ELF gets loaded into virtual addresses > */ > - cpu_reset(env); > + cpu_state_reset(env); > } > > ram = g_malloc(sizeof(*ram)); > diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c > index 104e5dc..445cfde 100644 > --- a/hw/xtensa_sim.c > +++ b/hw/xtensa_sim.c > @@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) > > static void sim_reset(void *env) > { > - cpu_reset(env); > + cpu_state_reset(env); > } > > static void sim_init(ram_addr_t ram_size, > diff --git a/linux-user/main.c b/linux-user/main.c > index bd47489..01129f2 100644 > --- a/linux-user/main.c > +++ b/linux-user/main.c > @@ -3375,7 +3375,7 @@ int main(int argc, char **argv, char **envp) > exit(1); > } > #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) > - cpu_reset(env); > + cpu_state_reset(env); > #endif > > thread_env = env; > diff --git a/linux-user/syscall.c b/linux-user/syscall.c > index 8a11213..29888bd 100644 > --- a/linux-user/syscall.c > +++ b/linux-user/syscall.c > @@ -4036,7 +4036,7 @@ static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp, > /* we create a new CPU instance. */ > new_env = cpu_copy(env); > #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) > - cpu_reset(new_env); > + cpu_state_reset(new_env); > #endif > /* Init regs that differ from the parent. */ > cpu_clone_regs(new_env, newsp); > diff --git a/target-arm/helper.c b/target-arm/helper.c > index abe1c30..13ff474 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -278,7 +278,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) > } > } > > -void cpu_reset(CPUARMState *env) > +void cpu_state_reset(CPUARMState *env) > { > uint32_t id; > uint32_t tmp = 0; > @@ -416,7 +416,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model) > > env->cpu_model_str = cpu_model; > env->cp15.c0_cpuid = id; > - cpu_reset(env); > + cpu_state_reset(env); > if (arm_feature(env, ARM_FEATURE_NEON)) { > gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, > 51, "arm-neon.xml", 0); > diff --git a/target-cris/translate.c b/target-cris/translate.c > index cbdc72c..f360c31 100644 > --- a/target-cris/translate.c > +++ b/target-cris/translate.c > @@ -3513,7 +3513,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model) > > env->pregs[PR_VR] = vr_by_name(cpu_model); > cpu_exec_init(env); > - cpu_reset(env); > + cpu_state_reset(env); > qemu_init_vcpu(env); > > if (tcg_initialized) > @@ -3573,7 +3573,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model) > return env; > } > > -void cpu_reset (CPUCRISState *env) > +void cpu_state_reset(CPUCRISState *env) > { > uint32_t vr; > > diff --git a/target-i386/helper.c b/target-i386/helper.c > index af6bba2..0d84c27 100644 > --- a/target-i386/helper.c > +++ b/target-i386/helper.c > @@ -27,7 +27,7 @@ > //#define DEBUG_MMU > > /* NOTE: must be called outside the CPU execute loop */ > -void cpu_reset(CPUX86State *env) > +void cpu_state_reset(CPUState *env) > { > int i; > > @@ -1281,7 +1281,7 @@ void do_cpu_init(CPUState *env) > int sipi = env->interrupt_request& CPU_INTERRUPT_SIPI; > uint64_t pat = env->pat; > > - cpu_reset(env); > + cpu_state_reset(env); > env->interrupt_request = sipi; > env->pat = pat; > apic_init_reset(env->apic_state); > diff --git a/target-lm32/helper.c b/target-lm32/helper.c > index 2637c03..6834401 100644 > --- a/target-lm32/helper.c > +++ b/target-lm32/helper.c > @@ -212,7 +212,7 @@ CPUState *cpu_lm32_init(const char *cpu_model) > env->flags = 0; > > cpu_exec_init(env); > - cpu_reset(env); > + cpu_state_reset(env); > qemu_init_vcpu(env); > > if (!tcg_initialized) { > @@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value) > } > } > > -void cpu_reset(CPUState *env) > +void cpu_state_reset(CPUState *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > diff --git a/target-m68k/helper.c b/target-m68k/helper.c > index fa675bf..3647366 100644 > --- a/target-m68k/helper.c > +++ b/target-m68k/helper.c > @@ -143,7 +143,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name) > return 0; > } > > -void cpu_reset(CPUM68KState *env) > +void cpu_state_reset(CPUM68KState *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > @@ -181,7 +181,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) > return NULL; > } > > - cpu_reset(env); > + cpu_state_reset(env); > qemu_init_vcpu(env); > return env; > } > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index 725c2dd..e34e88d 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -1897,7 +1897,7 @@ CPUState *cpu_mb_init (const char *cpu_model) > env = g_malloc0(sizeof(CPUState)); > > cpu_exec_init(env); > - cpu_reset(env); > + cpu_state_reset(env); > qemu_init_vcpu(env); > set_float_rounding_mode(float_round_nearest_even,&env->fp_status); > > @@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model) > return env; > } > > -void cpu_reset (CPUState *env) > +void cpu_state_reset(CPUState *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > diff --git a/target-mips/helper.c b/target-mips/helper.c > index 7225616..4d1cf98 100644 > --- a/target-mips/helper.c > +++ b/target-mips/helper.c > @@ -452,7 +452,7 @@ void do_interrupt (CPUState *env) > set_hflags_for_handler(env); > break; > case EXCP_RESET: > - cpu_reset(env); > + cpu_state_reset(env); > break; > case EXCP_SRESET: > env->CP0_Status |= (1<< CP0St_SR); > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 8361d88..5061e78 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -12708,12 +12708,12 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model) > fpu_init(env, def); > mvp_init(env, def); > mips_tcg_init(); > - cpu_reset(env); > + cpu_state_reset(env); > qemu_init_vcpu(env); > return env; > } > > -void cpu_reset (CPUMIPSState *env) > +void cpu_state_reset(CPUMIPSState *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > diff --git a/target-ppc/helper.c b/target-ppc/helper.c > index bb76a8b..f4552e8 100644 > --- a/target-ppc/helper.c > +++ b/target-ppc/helper.c > @@ -3136,7 +3136,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr) > TARGET_FMT_lx "\n", RA, msr); > } > > -void cpu_reset(CPUPPCState *env) > +void cpu_state_reset(CPUPPCState *env) > { > target_ulong msr; > > diff --git a/target-s390x/helper.c b/target-s390x/helper.c > index c0ec890..1a1cc0eb 100644 > --- a/target-s390x/helper.c > +++ b/target-s390x/helper.c > @@ -95,7 +95,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model) > env->cpu_model_str = cpu_model; > env->cpu_num = cpu_num++; > env->ext_index = -1; > - cpu_reset(env); > + cpu_state_reset(env); > qemu_init_vcpu(env); > return env; > } > @@ -119,7 +119,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw, > > #endif /* CONFIG_USER_ONLY */ > > -void cpu_reset(CPUS390XState *env) > +void cpu_state_reset(CPUS390XState *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > diff --git a/target-sh4/translate.c b/target-sh4/translate.c > index dd0ee4b..c385de8 100644 > --- a/target-sh4/translate.c > +++ b/target-sh4/translate.c > @@ -178,7 +178,7 @@ void cpu_dump_state(CPUState * env, FILE * f, > } > } > > -void cpu_reset(CPUSH4State * env) > +void cpu_state_reset(CPUSH4State *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > @@ -279,7 +279,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) > env->movcal_backup_tail =&(env->movcal_backup); > sh4_translate_init(); > env->cpu_model_str = cpu_model; > - cpu_reset(env); > + cpu_state_reset(env); > cpu_register(env, def); > qemu_init_vcpu(env); > return env; > diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c > index c7269b5..bb8b761 100644 > --- a/target-sparc/cpu_init.c > +++ b/target-sparc/cpu_init.c > @@ -23,7 +23,7 @@ > > static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); > > -void cpu_reset(CPUSPARCState *env) > +void cpu_state_reset(CPUSPARCState *env) > { > if (qemu_loglevel_mask(CPU_LOG_RESET)) { > qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); > diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c > index 42a559f..077c20a 100644 > --- a/target-xtensa/helper.c > +++ b/target-xtensa/helper.c > @@ -35,7 +35,7 @@ > > static void reset_mmu(CPUState *env); > > -void cpu_reset(CPUXtensaState *env) > +void cpu_state_reset(CPUXtensaState *env) > { > env->exception_taken = 0; > env->pc = env->config->exception_vector[EXC_RESET];
diff --git a/bsd-user/main.c b/bsd-user/main.c index cdb0d0a..c3af395 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -917,7 +917,7 @@ int main(int argc, char **argv) exit(1); } #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) - cpu_reset(env); + cpu_state_reset(env); #endif thread_env = env; diff --git a/cpu-all.h b/cpu-all.h index 80e6d42..7586c0d 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -433,7 +433,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask); #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ void cpu_single_step(CPUState *env, int enabled); -void cpu_reset(CPUState *s); +void cpu_state_reset(CPUState *s); int cpu_is_stopped(CPUState *env); void run_on_cpu(CPUState *env, void (*func)(void *data), void *data); diff --git a/cpu-exec.c b/cpu-exec.c index 3d28053..2bf1735 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -340,7 +340,7 @@ int cpu_exec(CPUState *env) } #elif defined(TARGET_PPC) if ((interrupt_request & CPU_INTERRUPT_RESET)) { - cpu_reset(env); + cpu_state_reset(env); } if (interrupt_request & CPU_INTERRUPT_HARD) { ppc_hw_interrupt(env); diff --git a/darwin-user/main.c b/darwin-user/main.c index e1519c7..13c1f05 100644 --- a/darwin-user/main.c +++ b/darwin-user/main.c @@ -858,7 +858,7 @@ int main(int argc, char **argv) /* NOTE: we need to init the CPU at this stage to get qemu_host_page_size */ env = cpu_init(cpu_model); - cpu_reset(env); + cpu_state_reset(env); printf("Starting %s with qemu\n----------------\n", filename); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index fc66910..23b3f0a 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -277,7 +277,7 @@ static void do_cpu_reset(void *opaque) CPUState *env = opaque; const struct arm_boot_info *info = env->boot_info; - cpu_reset(env); + cpu_state_reset(env); if (info) { if (!info->is_linux) { /* Jump to the entry point. */ diff --git a/hw/armv7m.c b/hw/armv7m.c index 6b80579..9cf96f4 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -149,7 +149,7 @@ static void armv7m_bitband_init(void) static void armv7m_reset(void *opaque) { - cpu_reset((CPUState *)opaque); + cpu_state_reset((CPUState *)opaque); } /* Init CPU and memory for a v7-M based board. diff --git a/hw/cris-boot.c b/hw/cris-boot.c index 37894f8..ade517d 100644 --- a/hw/cris-boot.c +++ b/hw/cris-boot.c @@ -34,7 +34,7 @@ static void main_cpu_reset(void *opaque) li = env->load_info; - cpu_reset(env); + cpu_state_reset(env); if (!li) { /* nothing more to do. */ diff --git a/hw/leon3.c b/hw/leon3.c index 71d79a6..1dc5a02 100644 --- a/hw/leon3.c +++ b/hw/leon3.c @@ -51,7 +51,7 @@ static void main_cpu_reset(void *opaque) ResetData *s = (ResetData *)opaque; CPUState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->halted = 0; env->pc = s->entry; diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c index 3cdf120..51c8a0f 100644 --- a/hw/lm32_boards.c +++ b/hw/lm32_boards.c @@ -56,7 +56,7 @@ static void main_cpu_reset(void *opaque) ResetInfo *reset_info = opaque; CPUState *env = reset_info->env; - cpu_reset(env); + cpu_state_reset(env); /* init defaults */ env->pc = (uint32_t)reset_info->bootstrap_pc; diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c index b2f96df..7ce04dc 100644 --- a/hw/microblaze_boot.c +++ b/hw/microblaze_boot.c @@ -45,7 +45,7 @@ static void main_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->regs[5] = boot_info.cmdline; env->regs[7] = boot_info.fdt; env->sregs[SR_PC] = boot_info.bootstrap_pc; diff --git a/hw/milkymist.c b/hw/milkymist.c index eaef0c2..7ec6554 100644 --- a/hw/milkymist.c +++ b/hw/milkymist.c @@ -61,7 +61,7 @@ static void main_cpu_reset(void *opaque) ResetInfo *reset_info = opaque; CPUState *env = reset_info->env; - cpu_reset(env); + cpu_state_reset(env); /* init defaults */ env->pc = reset_info->bootstrap_pc; diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c index e3ba9dd..2db8ba0 100644 --- a/hw/mips_fulong2e.c +++ b/hw/mips_fulong2e.c @@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); /* TODO: 2E reset stuff */ if (loaderparams.kernel_filename) { env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index 2b4678e..d5f1b34 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -51,7 +51,7 @@ enum jazz_model_e static void main_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); } static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index b1563ed..887faea 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -746,7 +746,7 @@ static void malta_mips_config(CPUState *env) static void main_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); /* The bootloader does not need to be rewritten as it is located in a read only location. The kernel location and the arguments table diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index 76c95b2..1fe4ac5 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -107,7 +107,7 @@ static void main_cpu_reset(void *opaque) ResetData *s = (ResetData *)opaque; CPUState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->active_tc.PC = s->vector & ~(target_ulong)1; if (s->vector & 1) { env->hflags |= MIPS_HFLAG_M16; diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index 83401f0..96ad808 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -145,7 +145,7 @@ static void main_cpu_reset(void *opaque) ResetData *s = (ResetData *)opaque; CPUState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->active_tc.PC = s->vector; } diff --git a/hw/omap1.c b/hw/omap1.c index 1aa5f23..5317b9b 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -3702,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque) omap_lpg_reset(mpu->led[0]); omap_lpg_reset(mpu->led[1]); omap_clkm_reset(mpu); - cpu_reset(mpu->env); + cpu_state_reset(mpu->env); } static const struct omap_map_s { diff --git a/hw/omap2.c b/hw/omap2.c index a6851b0..157defb 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -2224,7 +2224,7 @@ static void omap2_mpu_reset(void *opaque) omap_mcspi_reset(mpu->mcspi[1]); omap_i2c_reset(mpu->i2c[0]); omap_i2c_reset(mpu->i2c[1]); - cpu_reset(mpu->env); + cpu_state_reset(mpu->env); } static int omap2_validate_addr(struct omap_mpu_state_s *s, diff --git a/hw/pc.c b/hw/pc.c index bb9867b..aca4460 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -928,7 +928,7 @@ static void pc_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->halted = !cpu_is_bsp(env); } diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index f86b168..835e36d 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -147,7 +147,7 @@ static void main_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->gpr[1] = (16<<20) - 8; env->gpr[3] = FDT_ADDR; env->nip = entry; diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 26040ac..2311162 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -38,6 +38,13 @@ # define LOG_UIC(...) do { } while (0) #endif +static void ppc4xx_reset(void *opaque) +{ + CPUState *env = opaque; + + cpu_state_reset(env); +} + /*****************************************************************************/ /* Generic PowerPC 4xx processor instantiation */ CPUState *ppc4xx_init (const char *cpu_model, @@ -60,7 +67,7 @@ CPUState *ppc4xx_init (const char *cpu_model, tb_clk->opaque = env; ppc_dcr_init(env, NULL, NULL); /* Register qemu callbacks */ - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc4xx_reset, env); return env; } diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 506187b..fd8e21d 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -122,6 +122,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; } +static void ppc_core99_reset(void *opaque) +{ + CPUState *env = opaque; + + cpu_state_reset(env); +} + /* PowerPC Mac99 hardware initialisation */ static void ppc_core99_init (ram_addr_t ram_size, const char *boot_device, @@ -167,7 +174,7 @@ static void ppc_core99_init (ram_addr_t ram_size, } /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc_core99_reset, env); } /* allocate RAM */ diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 9295a34..085b825 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -66,6 +66,13 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; } +static void ppc_heathrow_reset(void *opaque) +{ + CPUState *env = opaque; + + cpu_state_reset(env); +} + static void ppc_heathrow_init (ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, @@ -105,7 +112,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, } /* Set time-base frequency to 16.6 Mhz */ cpu_ppc_tb_init(env, 16600000UL); - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc_heathrow_reset, env); } /* allocate RAM */ diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index eb43fb5..c5f2542 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -471,6 +471,13 @@ static void cpu_request_exit(void *opaque, int irq, int level) } } +static void ppc_prep_reset(void *opaque) +{ + CPUState *env = opaque; + + cpu_state_reset(env); +} + /* PowerPC PREP hardware initialisation */ static void ppc_prep_init (ram_addr_t ram_size, const char *boot_device, @@ -525,7 +532,7 @@ static void ppc_prep_init (ram_addr_t ram_size, /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); } - qemu_register_reset((QEMUResetHandler*)&cpu_reset, env); + qemu_register_reset(ppc_prep_reset, env); } /* allocate RAM */ diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index d69f78c..752aed9 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -198,7 +198,7 @@ static void mpc8544ds_cpu_reset_sec(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ @@ -211,7 +211,7 @@ static void mpc8544ds_cpu_reset(void *opaque) CPUState *env = opaque; struct boot_info *bi = env->load_info; - cpu_reset(env); + cpu_state_reset(env); /* Set initial guest state. */ env->halted = 0; diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 1ab2701..f552877 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -2045,7 +2045,7 @@ static void pxa2xx_reset(void *opaque, int line, int level) PXA2xxState *s = (PXA2xxState *) opaque; if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ - cpu_reset(s->env); + cpu_state_reset(s->env); /* TODO: reset peripherals */ } } diff --git a/hw/r2d.c b/hw/r2d.c index c80f9e3..ae327a7 100644 --- a/hw/r2d.c +++ b/hw/r2d.c @@ -201,7 +201,7 @@ static void main_cpu_reset(void *opaque) ResetData *s = (ResetData *)opaque; CPUState *env = s->env; - cpu_reset(env); + cpu_state_reset(env); env->pc = s->vector; } diff --git a/hw/spapr.c b/hw/spapr.c index dffb6a2..3f9d87c 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -502,6 +502,13 @@ static void spapr_reset(void *opaque) } +static void spapr_cpu_reset(void *opaque) +{ + CPUState *env = opaque; + + cpu_state_reset(env); +} + /* pSeries LPAR / sPAPR hardware init */ static void ppc_spapr_init(ram_addr_t ram_size, const char *boot_device, @@ -560,7 +567,7 @@ static void ppc_spapr_init(ram_addr_t ram_size, } /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, TIMEBASE_FREQ); - qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); + qemu_register_reset(spapr_cpu_reset, env); env->hreset_vector = 0x60; env->hreset_excp_prefix = 0; diff --git a/hw/sun4m.c b/hw/sun4m.c index 99fb219..4045740 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -283,7 +283,7 @@ static void main_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->halted = 0; } @@ -291,7 +291,7 @@ static void secondary_cpu_reset(void *opaque) { CPUState *env = opaque; - cpu_reset(env); + cpu_state_reset(env); env->halted = 1; } diff --git a/hw/sun4u.c b/hw/sun4u.c index 423108f..8b043f2 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -376,7 +376,7 @@ static void main_cpu_reset(void *opaque) CPUState *env = s->env; static unsigned int nr_resets; - cpu_reset(env); + cpu_state_reset(env); cpu_timer_reset(env->tick); cpu_timer_reset(env->stick); diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c index f8d2b1b..e672490 100644 --- a/hw/virtex_ml507.c +++ b/hw/virtex_ml507.c @@ -109,7 +109,7 @@ static void main_cpu_reset(void *opaque) CPUState *env = opaque; struct boot_info *bi = env->load_info; - cpu_reset(env); + cpu_state_reset(env); /* Linux Kernel Parameters (passing device tree): * r3: pointer to the fdt * r4: 0 diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c index 26112c3..80ba4d7 100644 --- a/hw/xtensa_lx60.c +++ b/hw/xtensa_lx60.c @@ -146,9 +146,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) return cpu_get_phys_page_debug(env, addr); } -static void lx60_reset(void *env) +static void lx60_reset(void *opaque) { - cpu_reset(env); + CPUState *env = opaque; + + cpu_state_reset(env); } static void lx_init(const LxBoardDesc *board, @@ -183,7 +185,7 @@ static void lx_init(const LxBoardDesc *board, /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ - cpu_reset(env); + cpu_state_reset(env); } ram = g_malloc(sizeof(*ram)); diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c index 104e5dc..445cfde 100644 --- a/hw/xtensa_sim.c +++ b/hw/xtensa_sim.c @@ -39,7 +39,7 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) static void sim_reset(void *env) { - cpu_reset(env); + cpu_state_reset(env); } static void sim_init(ram_addr_t ram_size, diff --git a/linux-user/main.c b/linux-user/main.c index bd47489..01129f2 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3375,7 +3375,7 @@ int main(int argc, char **argv, char **envp) exit(1); } #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) - cpu_reset(env); + cpu_state_reset(env); #endif thread_env = env; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 8a11213..29888bd 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4036,7 +4036,7 @@ static int do_fork(CPUState *env, unsigned int flags, abi_ulong newsp, /* we create a new CPU instance. */ new_env = cpu_copy(env); #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) - cpu_reset(new_env); + cpu_state_reset(new_env); #endif /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); diff --git a/target-arm/helper.c b/target-arm/helper.c index abe1c30..13ff474 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -278,7 +278,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) } } -void cpu_reset(CPUARMState *env) +void cpu_state_reset(CPUARMState *env) { uint32_t id; uint32_t tmp = 0; @@ -416,7 +416,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model) env->cpu_model_str = cpu_model; env->cp15.c0_cpuid = id; - cpu_reset(env); + cpu_state_reset(env); if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); diff --git a/target-cris/translate.c b/target-cris/translate.c index cbdc72c..f360c31 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3513,7 +3513,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model) env->pregs[PR_VR] = vr_by_name(cpu_model); cpu_exec_init(env); - cpu_reset(env); + cpu_state_reset(env); qemu_init_vcpu(env); if (tcg_initialized) @@ -3573,7 +3573,7 @@ CPUCRISState *cpu_cris_init (const char *cpu_model) return env; } -void cpu_reset (CPUCRISState *env) +void cpu_state_reset(CPUCRISState *env) { uint32_t vr; diff --git a/target-i386/helper.c b/target-i386/helper.c index af6bba2..0d84c27 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -27,7 +27,7 @@ //#define DEBUG_MMU /* NOTE: must be called outside the CPU execute loop */ -void cpu_reset(CPUX86State *env) +void cpu_state_reset(CPUState *env) { int i; @@ -1281,7 +1281,7 @@ void do_cpu_init(CPUState *env) int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI; uint64_t pat = env->pat; - cpu_reset(env); + cpu_state_reset(env); env->interrupt_request = sipi; env->pat = pat; apic_init_reset(env->apic_state); diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 2637c03..6834401 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -212,7 +212,7 @@ CPUState *cpu_lm32_init(const char *cpu_model) env->flags = 0; cpu_exec_init(env); - cpu_reset(env); + cpu_state_reset(env); qemu_init_vcpu(env); if (!tcg_initialized) { @@ -235,7 +235,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value) } } -void cpu_reset(CPUState *env) +void cpu_state_reset(CPUState *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); diff --git a/target-m68k/helper.c b/target-m68k/helper.c index fa675bf..3647366 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -143,7 +143,7 @@ static int cpu_m68k_set_model(CPUM68KState *env, const char *name) return 0; } -void cpu_reset(CPUM68KState *env) +void cpu_state_reset(CPUM68KState *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -181,7 +181,7 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model) return NULL; } - cpu_reset(env); + cpu_state_reset(env); qemu_init_vcpu(env); return env; } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 725c2dd..e34e88d 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1897,7 +1897,7 @@ CPUState *cpu_mb_init (const char *cpu_model) env = g_malloc0(sizeof(CPUState)); cpu_exec_init(env); - cpu_reset(env); + cpu_state_reset(env); qemu_init_vcpu(env); set_float_rounding_mode(float_round_nearest_even, &env->fp_status); @@ -1939,7 +1939,7 @@ CPUState *cpu_mb_init (const char *cpu_model) return env; } -void cpu_reset (CPUState *env) +void cpu_state_reset(CPUState *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); diff --git a/target-mips/helper.c b/target-mips/helper.c index 7225616..4d1cf98 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -452,7 +452,7 @@ void do_interrupt (CPUState *env) set_hflags_for_handler(env); break; case EXCP_RESET: - cpu_reset(env); + cpu_state_reset(env); break; case EXCP_SRESET: env->CP0_Status |= (1 << CP0St_SR); diff --git a/target-mips/translate.c b/target-mips/translate.c index 8361d88..5061e78 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12708,12 +12708,12 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model) fpu_init(env, def); mvp_init(env, def); mips_tcg_init(); - cpu_reset(env); + cpu_state_reset(env); qemu_init_vcpu(env); return env; } -void cpu_reset (CPUMIPSState *env) +void cpu_state_reset(CPUMIPSState *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); diff --git a/target-ppc/helper.c b/target-ppc/helper.c index bb76a8b..f4552e8 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -3136,7 +3136,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr) TARGET_FMT_lx "\n", RA, msr); } -void cpu_reset(CPUPPCState *env) +void cpu_state_reset(CPUPPCState *env) { target_ulong msr; diff --git a/target-s390x/helper.c b/target-s390x/helper.c index c0ec890..1a1cc0eb 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -95,7 +95,7 @@ CPUS390XState *cpu_s390x_init(const char *cpu_model) env->cpu_model_str = cpu_model; env->cpu_num = cpu_num++; env->ext_index = -1; - cpu_reset(env); + cpu_state_reset(env); qemu_init_vcpu(env); return env; } @@ -119,7 +119,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw, #endif /* CONFIG_USER_ONLY */ -void cpu_reset(CPUS390XState *env) +void cpu_state_reset(CPUS390XState *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index dd0ee4b..c385de8 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -178,7 +178,7 @@ void cpu_dump_state(CPUState * env, FILE * f, } } -void cpu_reset(CPUSH4State * env) +void cpu_state_reset(CPUSH4State *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); @@ -279,7 +279,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) env->movcal_backup_tail = &(env->movcal_backup); sh4_translate_init(); env->cpu_model_str = cpu_model; - cpu_reset(env); + cpu_state_reset(env); cpu_register(env, def); qemu_init_vcpu(env); return env; diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c index c7269b5..bb8b761 100644 --- a/target-sparc/cpu_init.c +++ b/target-sparc/cpu_init.c @@ -23,7 +23,7 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); -void cpu_reset(CPUSPARCState *env) +void cpu_state_reset(CPUSPARCState *env) { if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 42a559f..077c20a 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -35,7 +35,7 @@ static void reset_mmu(CPUState *env); -void cpu_reset(CPUXtensaState *env) +void cpu_state_reset(CPUXtensaState *env) { env->exception_taken = 0; env->pc = env->config->exception_vector[EXC_RESET];
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: Andreas Färber <afaerber@suse.de> --- bsd-user/main.c | 2 +- cpu-all.h | 2 +- cpu-exec.c | 2 +- darwin-user/main.c | 2 +- hw/arm_boot.c | 2 +- hw/armv7m.c | 2 +- hw/cris-boot.c | 2 +- hw/leon3.c | 2 +- hw/lm32_boards.c | 2 +- hw/microblaze_boot.c | 2 +- hw/milkymist.c | 2 +- hw/mips_fulong2e.c | 2 +- hw/mips_jazz.c | 2 +- hw/mips_malta.c | 2 +- hw/mips_mipssim.c | 2 +- hw/mips_r4k.c | 2 +- hw/omap1.c | 2 +- hw/omap2.c | 2 +- hw/pc.c | 2 +- hw/ppc440_bamboo.c | 2 +- hw/ppc4xx_devs.c | 9 ++++++++- hw/ppc_newworld.c | 9 ++++++++- hw/ppc_oldworld.c | 9 ++++++++- hw/ppc_prep.c | 9 ++++++++- hw/ppce500_mpc8544ds.c | 4 ++-- hw/pxa2xx.c | 2 +- hw/r2d.c | 2 +- hw/spapr.c | 9 ++++++++- hw/sun4m.c | 4 ++-- hw/sun4u.c | 2 +- hw/virtex_ml507.c | 2 +- hw/xtensa_lx60.c | 8 +++++--- hw/xtensa_sim.c | 2 +- linux-user/main.c | 2 +- linux-user/syscall.c | 2 +- target-arm/helper.c | 4 ++-- target-cris/translate.c | 4 ++-- target-i386/helper.c | 4 ++-- target-lm32/helper.c | 4 ++-- target-m68k/helper.c | 4 ++-- target-microblaze/translate.c | 4 ++-- target-mips/helper.c | 2 +- target-mips/translate.c | 4 ++-- target-ppc/helper.c | 2 +- target-s390x/helper.c | 4 ++-- target-sh4/translate.c | 4 ++-- target-sparc/cpu_init.c | 2 +- target-xtensa/helper.c | 2 +- 48 files changed, 98 insertions(+), 61 deletions(-)