From patchwork Thu Mar 8 13:56:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 145527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8C0EDB6FA1 for ; Fri, 9 Mar 2012 00:56:50 +1100 (EST) Received: from localhost ([::1]:39505 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S5dpo-0006N8-GG for incoming@patchwork.ozlabs.org; Thu, 08 Mar 2012 08:56:48 -0500 Received: from eggs.gnu.org ([208.118.235.92]:38975) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S5dpi-0006Mt-1w for qemu-devel@nongnu.org; Thu, 08 Mar 2012 08:56:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S5dpb-0004hU-EG for qemu-devel@nongnu.org; Thu, 08 Mar 2012 08:56:41 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:52607) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S5dpb-0004gh-4P for qemu-devel@nongnu.org; Thu, 08 Mar 2012 08:56:35 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1S5dpS-0007UD-NU; Thu, 08 Mar 2012 13:56:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 8 Mar 2012 13:56:26 +0000 Message-Id: <1331214986-28754-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH] ARM: Remove unnecessary subpage workarounds X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In the ARM per-CPU peripherals (GIC, private timers, SCU, etc), remove workarounds for subpage memory region read/write functions being passed offsets from the start of the page rather than the start of the region. Following commit 5312bd8b3 the masking off of high bits of the address offset is now harmless but unnecessary. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- hw/arm11mpcore.c | 2 -- hw/arm_gic.c | 8 ++++---- hw/arm_mptimer.c | 2 -- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index c67b70f..ba6a89d 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -42,7 +42,6 @@ static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset, { mpcore_priv_state *s = (mpcore_priv_state *)opaque; int id; - offset &= 0xff; /* SCU */ switch (offset) { case 0x00: /* Control. */ @@ -63,7 +62,6 @@ static void mpcore_scu_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { mpcore_priv_state *s = (mpcore_priv_state *)opaque; - offset &= 0xff; /* SCU */ switch (offset) { case 0: /* Control register. */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index d8a7a19..6b34c06 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -658,14 +658,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, unsigned size) { gic_state *s = (gic_state *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff); + return gic_cpu_read(s, gic_get_current_cpu(), addr); } static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { gic_state *s = (gic_state *)opaque; - gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value); + gic_cpu_write(s, gic_get_current_cpu(), addr, value); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -677,7 +677,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, gic_state **backref = (gic_state **)opaque; gic_state *s = *backref; int id = (backref - s->backref); - return gic_cpu_read(s, id, addr & 0xff); + return gic_cpu_read(s, id, addr); } static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, @@ -686,7 +686,7 @@ static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, gic_state **backref = (gic_state **)opaque; gic_state *s = *backref; int id = (backref - s->backref); - gic_cpu_write(s, id, addr & 0xff, value); + gic_cpu_write(s, id, addr, value); } static const MemoryRegionOps gic_thiscpu_ops = { diff --git a/hw/arm_mptimer.c b/hw/arm_mptimer.c index 361e887..df7fb4c 100644 --- a/hw/arm_mptimer.c +++ b/hw/arm_mptimer.c @@ -97,7 +97,6 @@ static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr, { timerblock *tb = (timerblock *)opaque; int64_t val; - addr &= 0x1f; switch (addr) { case 0: /* Load */ return tb->load; @@ -126,7 +125,6 @@ static void timerblock_write(void *opaque, target_phys_addr_t addr, { timerblock *tb = (timerblock *)opaque; int64_t old; - addr &= 0x1f; switch (addr) { case 0: /* Load */ tb->load = value;