From patchwork Tue Feb 28 03:51:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 143324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 25104B6FA4 for ; Tue, 28 Feb 2012 14:51:42 +1100 (EST) Received: from localhost ([::1]:33765 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2E6F-0006y2-LG for incoming@patchwork.ozlabs.org; Mon, 27 Feb 2012 22:51:39 -0500 Received: from eggs.gnu.org ([208.118.235.92]:44619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2E69-0006xV-0D for qemu-devel@nongnu.org; Mon, 27 Feb 2012 22:51:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S2E66-0006Fu-Sv for qemu-devel@nongnu.org; Mon, 27 Feb 2012 22:51:32 -0500 Received: from ozlabs.org ([203.10.76.45]:39357) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S2E66-0006Fn-8x for qemu-devel@nongnu.org; Mon, 27 Feb 2012 22:51:30 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id AC272B6FA4; Tue, 28 Feb 2012 14:51:26 +1100 (EST) From: David Gibson To: kraxel@redhat.com Date: Tue, 28 Feb 2012 14:51:22 +1100 Message-Id: <1330401082-10073-1-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.9 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 203.10.76.45 Cc: Wei Yang , qemu-devel@nongnu.org, anthony@codemonkey.ws, David Gibson Subject: [Qemu-devel] [PATCH] USB OHCI bug fixes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch fixes two bugs in the OHCI device where the device writes back data to system memory that should be exclusively under the control of the guest side driver. In OHCI specification Section 5.2.7, it mentioned "In all cases, Host Controller Driver is responsible for the insertion and removal of all Endpoint Descriptors in the various Host Controller Endpoint Descriptor lists". In the ohci_frame_boundary(), ohci_put_hcca() writes the entire hcca back including the interrupt ED lists which should be under driver control. This violates the specification and can race with a host driver updating that list at the same time. In the OHCI Spec Section 4.6, Transfer Descriptor Queue Processing, it mentioned "Since the TD pointed to by TailP is not accessed by the HC, the Host Controller Driver can initialize that TD and link at least one other to it without creating a coherency or synchronization problem". While the function ohci_put_ed() writes the entire endpoint descriptor back including the TailP which should under driver control. This violate the specification and can race with a host driver updating the TD list at the same time. In each case the solution is to make sure we don't write data which is under driver control. Cc: Gerd Hoffman Signed-off-by: Wei Yang Signed-off-by: David Gibson --- hw/usb-ohci.c | 21 +++++++++++++++++++-- 1 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c index 7aa19fe..c0ffc3b 100644 --- a/hw/usb-ohci.c +++ b/hw/usb-ohci.c @@ -122,6 +122,11 @@ struct ohci_hcca { uint16_t frame, pad; uint32_t done; }; +#define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) +#define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ + +#define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) +#define ED_WBACK_SIZE 4 static void ohci_bus_stop(OHCIState *ohci); static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); @@ -189,6 +194,10 @@ struct ohci_ed { uint32_t head; uint32_t next; }; +#define ED_TAILP_OFFSET offsetof(struct ohci_ed, tail) +#define ED_PART1_SIZE ED_TAILP_OFFSET +#define ED_HEADP_OFFSET offsetof(struct ohci_ed, head) +#define ED_PART2_SIZE (sizeof(struct ohci_ed) - ED_HEADP_OFFSET) /* General transfer descriptor */ struct ohci_td { @@ -569,7 +578,13 @@ static inline int ohci_read_hcca(OHCIState *ohci, static inline int ohci_put_ed(OHCIState *ohci, uint32_t addr, struct ohci_ed *ed) { - return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); + /* ed->tail is under control of the HCD. + * Since just ed->head is changed by HC, just write back this + */ + + return put_dwords(ohci, addr + ED_WBACK_OFFSET, + (uint32_t *)((char *)ed + ED_WBACK_OFFSET), + ED_WBACK_SIZE >> 2); } static inline int ohci_put_td(OHCIState *ohci, @@ -588,7 +603,9 @@ static inline int ohci_put_iso_td(OHCIState *ohci, static inline int ohci_put_hcca(OHCIState *ohci, uint32_t addr, struct ohci_hcca *hcca) { - cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca)); + cpu_physical_memory_write(addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, + (char *)hcca + HCCA_WRITEBACK_OFFSET, + HCCA_WRITEBACK_SIZE); return 1; }