| Message ID | 1328237992-14953-15-git-send-email-afaerber@suse.de |
|---|---|
| State | New |
| Headers | show |
On 3 February 2012 03:59, Andreas Färber <afaerber@suse.de> wrote:
> No other emulated CPU uses this at this time.
But why does this code better fit in hw/ than target-arm? The iwMMXt
registers are core registers after all.
Also the defines let the board code request a cpu revision by name
instead of using a magic number, so I think they're useful.
Cheers
Am 17.02.2012 10:59, schrieb andrzej zaborowski: > On 3 February 2012 03:59, Andreas Färber <afaerber@suse.de> wrote: >> No other emulated CPU uses this at this time. > > But why does this code better fit in hw/ than target-arm? The iwMMXt > registers are core registers after all. It seems you've misread something here. This is all in target-arm. :) > Also the defines let the board code request a cpu revision by name > instead of using a magic number, so I think they're useful. No, the boards request a CPU by type name, which is not magic either. The whole point of QOM'ification is to have the CPU provide the necessary fields and methods, not logic spread across the code in an if-this-cpu-then fashion. I plan to tackle cp15 (the last remainder of CPUID code dependencies) when I'm through with all other targets. If someone really needs the CPUID they can access it through ARMCPU (CPUARMState). The final plan for rnpn is to have two QOM properties and to request a "pxa270" CPU, then set the revision since there are no functional dependencies on the revision at all. (cc'ing Paul) I've actually compile-tested and grep'ed this. Please note also the following v4 that came out of an IRC discussion: http://repo.or.cz/w/qemu/afaerber.git/commitdiff/1262acf06308cf2bde46520d0238548cb73c79fe If you need the JTAG_ID somewhere please let us know soon. Andreas
On 17 February 2012 13:03, Andreas Färber <afaerber@suse.de> wrote: > Am 17.02.2012 10:59, schrieb andrzej zaborowski: >> On 3 February 2012 03:59, Andreas Färber <afaerber@suse.de> wrote: >>> No other emulated CPU uses this at this time. >> >> But why does this code better fit in hw/ than target-arm? The iwMMXt >> registers are core registers after all. > > It seems you've misread something here. This is all in target-arm. :) Yes, I did, sorry. I had looked at the whole series previously, forgotten it, then looked at this patch that was still in my inbox without any of the context. ... > The final plan for rnpn is to have two QOM properties and to request a > "pxa270" CPU, then set the revision since there are no functional > dependencies on the revision at all. (cc'ing Paul) > I've actually compile-tested and grep'ed this. > Sounds reasonable. > > Please note also the following v4 that came out of an IRC discussion: > http://repo.or.cz/w/qemu/afaerber.git/commitdiff/1262acf06308cf2bde46520d0238548cb73c79fe > If you need the JTAG_ID somewhere please let us know soon. No, it's not used anywhere (obviously otherwise it wouldn't be a comment) Cheers
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7d4f0f6..bf4b272 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -229,8 +229,22 @@ static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info) set_class_feature(k, ARM_FEATURE_XSCALE); } +static void pxa270_reset(CPU *c) +{ + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + + arm_cpu_reset(c); + + env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; +} + static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info) { + CPUClass *cpu_class = CPU_CLASS(k); + + cpu_class->reset = pxa270_reset; + k->cp15.c0_cachetype = 0xd172172; k->cp15.c1_sys = 0x00000078; k->jtag_id = ((uint64_t)k->cp15.c0_cpuid << 28) | 0x09265013; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 351b057..32aaa4e 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -406,12 +406,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define ARM_CPUID_ARM926 0x41069265 #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPUID_PXA270_A0 0x69054110 -#define ARM_CPUID_PXA270_A1 0x69054111 -#define ARM_CPUID_PXA270_B0 0x69054112 -#define ARM_CPUID_PXA270_B1 0x69054113 -#define ARM_CPUID_PXA270_C0 0x69054114 -#define ARM_CPUID_PXA270_C5 0x69054117 #define ARM_CPUID_ARM1136 0x4117b363 #define ARM_CPUID_ARM1136_R2 0x4107b362 #define ARM_CPUID_ARM1176 0x410fb767 diff --git a/target-arm/helper.c b/target-arm/helper.c index bf28fea..4a531b8 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -76,14 +76,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; break; - case ARM_CPUID_PXA270_A0: - case ARM_CPUID_PXA270_A1: - case ARM_CPUID_PXA270_B0: - case ARM_CPUID_PXA270_B1: - case ARM_CPUID_PXA270_C0: - case ARM_CPUID_PXA270_C5: - env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; - break; default: break; }
No other emulated CPU uses this at this time. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Andrzej Zaborowski <balrogg@gmail.com> --- target-arm/cpu.c | 14 ++++++++++++++ target-arm/cpu.h | 6 ------ target-arm/helper.c | 8 -------- 3 files changed, 14 insertions(+), 14 deletions(-)