From patchwork Mon Sep 5 23:55:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 113445 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F0D82B6F7E for ; Tue, 6 Sep 2011 09:56:18 +1000 (EST) Received: from localhost ([::1]:43184 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1S-0002zS-S7 for incoming@patchwork.ozlabs.org; Mon, 05 Sep 2011 19:56:14 -0400 Received: from eggs.gnu.org ([140.186.70.92]:36760) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1D-0002yC-J1 for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:56:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R0j1C-0003Gr-FL for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:55:59 -0400 Received: from [188.134.19.124] (port=53290 helo=octofox.metropolis) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R0j1B-0003GG-QV for qemu-devel@nongnu.org; Mon, 05 Sep 2011 19:55:58 -0400 Received: from octofox.metropolis (localhost [127.0.0.1]) by octofox.metropolis (8.14.5/8.14.5) with ESMTP id p85Nu67u023028; Tue, 6 Sep 2011 03:56:06 +0400 Received: (from jcmvbkbc@localhost) by octofox.metropolis (8.14.5/8.14.5/Submit) id p85Nu6ct023027; Tue, 6 Sep 2011 03:56:06 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 6 Sep 2011 03:55:28 +0400 Message-Id: <1315266957-22979-5-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.6 In-Reply-To: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> References: <1315266957-22979-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 188.134.19.124 Cc: jcmvbkbc@gmail.com Subject: [Qemu-devel] [PATCH v5 04/33] target-xtensa: implement narrow instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 54 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 0524dc7..4dfca2b 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -106,6 +106,11 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) dc->is_jmp = DISAS_UPDATE; } +static void gen_jump(DisasContext *dc, TCGv dest) +{ + gen_jump_slot(dc, dest, -1); +} + static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) { TCGv_i32 tmp = tcg_const_i32(dest); @@ -377,22 +382,71 @@ static void disas_xtensa_insn(DisasContext *dc) case 7: /*B*/ break; +#define gen_narrow_load_store(type) do { \ + TCGv_i32 addr = tcg_temp_new_i32(); \ + tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \ + tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \ + tcg_temp_free(addr); \ + } while (0) + case 8: /*L32I.Nn*/ + gen_narrow_load_store(ld32u); break; case 9: /*S32I.Nn*/ + gen_narrow_load_store(st32); break; +#undef gen_narrow_load_store case 10: /*ADD.Nn*/ + tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]); break; case 11: /*ADDI.Nn*/ + tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1); break; case 12: /*ST2n*/ + if (RRRN_T < 8) { /*MOVI.Nn*/ + tcg_gen_movi_i32(cpu_R[RRRN_S], + RRRN_R | (RRRN_T << 4) | + ((RRRN_T & 6) == 6 ? 0xffffff80 : 0)); + } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/ + } break; case 13: /*ST3n*/ + switch (RRRN_R) { + case 0: /*MOV.Nn*/ + tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]); + break; + + case 15: /*S3*/ + switch (RRRN_T) { + case 0: /*RET.Nn*/ + gen_jump(dc, cpu_R[0]); + break; + + case 1: /*RETW.Nn*/ + break; + + case 2: /*BREAK.Nn*/ + break; + + case 3: /*NOP.Nn*/ + break; + + case 6: /*ILL.Nn*/ + break; + + default: /*reserved*/ + break; + } + break; + + default: /*reserved*/ + break; + } break; default: /*reserved*/