diff mbox

[26/35] target-alpha: Use a fixed frequency for the RPCC in system mode.

Message ID 1304976889-29675-27-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson May 9, 2011, 9:34 p.m. UTC 
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-alpha/cpu.h       |    2 --
 target-alpha/op_helper.c |   14 +++++++++++---
 2 files changed, 11 insertions(+), 5 deletions(-)
diff mbox

Patch

diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index d26a870..c94becf 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -256,7 +256,6 @@  struct CPUAlphaState {
     uint64_t trap_arg1;
     uint64_t trap_arg2;
 
-#if !defined(CONFIG_USER_ONLY)
     /* The internal data required by our emulation of the Unix PALcode.  */
     uint64_t exc_addr;
     uint64_t palbr;
@@ -266,7 +265,6 @@  struct CPUAlphaState {
     uint64_t usp;
     uint64_t shadow[8];
     uint64_t scratch[24];
-#endif
 
 #if TARGET_LONG_BITS > HOST_LONG_BITS
     /* temporary fixed-point registers
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 42fec07..36b8289 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -65,9 +65,17 @@  static void QEMU_NORETURN arith_excp(int exc, uint64_t mask)
 
 uint64_t helper_load_pcc (void)
 {
-    /* ??? This isn't a timer for which we have any rate info.  */
-    uint64_t ret = env->pcc_ofs;
-    return ret << 32 | (uint32_t)cpu_get_real_ticks();
+#ifndef CONFIG_USER_ONLY
+    /* In system mode we have access to a decent high-resolution clock.
+       In order to make OS-level time accounting work with the RPCC,
+       present it with a well-timed clock fixed at 250MHz.  */
+    return (((uint64_t)env->pcc_ofs << 32)
+            | (uint32_t)(qemu_get_clock_ns(vm_clock) >> 2));
+#else
+    /* In user-mode, vm_clock doesn't exist.  Just pass through the host cpu
+       clock ticks.  Also, don't bother taking PCC_OFS into account.  */
+    return (uint32_t)cpu_get_real_ticks();
+#endif
 }
 
 uint64_t helper_load_fpcr (void)