From patchwork Tue Jan 11 21:01:34 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 78446 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 42F9FB6EF2 for ; Wed, 12 Jan 2011 08:34:52 +1100 (EST) Received: from localhost ([127.0.0.1]:55459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pclrd-0000WA-7p for incoming@patchwork.ozlabs.org; Tue, 11 Jan 2011 16:34:49 -0500 Received: from [140.186.70.92] (port=33305 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PclMp-00036T-5O for qemu-devel@nongnu.org; Tue, 11 Jan 2011 16:03:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PclLd-0001ML-DL for qemu-devel@nongnu.org; Tue, 11 Jan 2011 16:02:50 -0500 Received: from hall.aurel32.net ([88.191.126.93]:47316) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PclLd-0001Lf-2j for qemu-devel@nongnu.org; Tue, 11 Jan 2011 16:01:45 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1PclLc-0001nb-Bv; Tue, 11 Jan 2011 22:01:44 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.72) (envelope-from ) id 1PclLd-0004f8-0p; Tue, 11 Jan 2011 22:01:45 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 11 Jan 2011 22:01:34 +0100 Message-Id: <1294779698-17694-6-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1294779698-17694-1-git-send-email-aurelien@aurel32.net> References: <1294779698-17694-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 5/9] target-sh4: define FPSCR constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno --- target-sh4/cpu.h | 35 +++++++++++++++++++++++++++++++---- target-sh4/op_helper.c | 7 ++++--- target-sh4/translate.c | 4 ++-- 3 files changed, 37 insertions(+), 9 deletions(-) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 8ccf25c..fe33b8a 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -61,10 +61,37 @@ #define SR_S (1 << 1) #define SR_T (1 << 0) -#define FPSCR_FR (1 << 21) -#define FPSCR_SZ (1 << 20) -#define FPSCR_PR (1 << 19) -#define FPSCR_DN (1 << 18) +#define FPSCR_MASK (0x003fffff) +#define FPSCR_FR (1 << 21) +#define FPSCR_SZ (1 << 20) +#define FPSCR_PR (1 << 19) +#define FPSCR_DN (1 << 18) +#define FPSCR_CAUSE_MASK (0x3f << 12) +#define FPSCR_CAUSE_SHIFT (12) +#define FPSCR_CAUSE_E (1 << 17) +#define FPSCR_CAUSE_V (1 << 16) +#define FPSCR_CAUSE_Z (1 << 15) +#define FPSCR_CAUSE_O (1 << 14) +#define FPSCR_CAUSE_U (1 << 13) +#define FPSCR_CAUSE_I (1 << 12) +#define FPSCR_ENABLE_MASK (0x1f << 7) +#define FPSCR_ENABLE_SHIFT (7) +#define FPSCR_ENABLE_V (1 << 11) +#define FPSCR_ENABLE_Z (1 << 10) +#define FPSCR_ENABLE_O (1 << 9) +#define FPSCR_ENABLE_U (1 << 8) +#define FPSCR_ENABLE_I (1 << 7) +#define FPSCR_FLAG_MASK (0x1f << 2) +#define FPSCR_FLAG_SHIFT (2) +#define FPSCR_FLAG_V (1 << 6) +#define FPSCR_FLAG_Z (1 << 5) +#define FPSCR_FLAG_O (1 << 4) +#define FPSCR_FLAG_U (1 << 3) +#define FPSCR_FLAG_I (1 << 2) +#define FPSCR_RM_MASK (0x03 << 0) +#define FPSCR_RM_NEAREST (0 << 0) +#define FPSCR_RM_ZERO (1 << 0) + #define DELAY_SLOT (1 << 0) #define DELAY_SLOT_CONDITIONAL (1 << 1) #define DELAY_SLOT_TRUE (1 << 2) diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index d8d0bb4..9915e42 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -428,11 +428,12 @@ static inline void clr_t(void) void helper_ld_fpscr(uint32_t val) { - env->fpscr = val & 0x003fffff; - if (val & 0x01) + env->fpscr = val & FPSCR_MASK; + if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) { set_float_rounding_mode(float_round_to_zero, &env->fp_status); - else + } else { set_float_rounding_mode(float_round_nearest_even, &env->fp_status); + } } uint32_t helper_fabs_FT(uint32_t t0) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 8d59bf9..bdfa31a 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -203,10 +203,10 @@ static void cpu_sh4_reset(CPUSH4State * env) env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ #else - env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ + env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ set_float_rounding_mode(float_round_to_zero, &env->fp_status); #endif - set_default_nan_mode(1, &env->vfp.fp_status); + set_default_nan_mode(1, &env->fp_status); env->mmucr = 0; }