From patchwork Fri Jan 7 09:26:26 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 77859 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1457DB70B3 for ; Fri, 7 Jan 2011 20:28:19 +1100 (EST) Received: from localhost ([127.0.0.1]:47198 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pb8cJ-00062k-TC for incoming@patchwork.ozlabs.org; Fri, 07 Jan 2011 04:28:16 -0500 Received: from [140.186.70.92] (port=43465 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pb8ac-00061l-JU for qemu-devel@nongnu.org; Fri, 07 Jan 2011 04:26:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pb8ab-0005so-2H for qemu-devel@nongnu.org; Fri, 07 Jan 2011 04:26:30 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:47395) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pb8aa-0005sS-Pv for qemu-devel@nongnu.org; Fri, 07 Jan 2011 04:26:29 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1Pb8aZ-0006KS-4G for qemu-devel@nongnu.org; Fri, 07 Jan 2011 09:26:27 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 7 Jan 2011 09:26:26 +0000 Message-Id: <1294392387-24300-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1294392387-24300-1-git-send-email-peter.maydell@linaro.org> References: <1294392387-24300-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH 3/4] target-arm: Add support for 'Standard FPSCR Value' as used by Neon X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support to the ARM helper routines for a second fp_status value which should be used for operations which the ARM ARM indicates use "ARM standard floating-point arithmetic" rather than being controlled by the rounding/flush/NaN settings in the FPSCR. Signed-off-by: Peter Maydell Reviewed-by: Aurelien Jarno --- target-arm/cpu.h | 13 +++++++++++++ target-arm/helper.c | 5 +++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 340933e..e501cf5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -173,7 +173,20 @@ typedef struct CPUARMState { /* scratch space when Tn are not sufficient. */ uint32_t scratch[8]; + /* fp_status is the "normal" fp status. standard_fp_status retains + * values corresponding to the ARM "Standard FPSCR Value", ie + * default-NaN, flush-to-zero, round-to-nearest and is used by + * any operations (generally Neon) which the architecture defines + * as controlled by the standard FPSCR value rather than the FPSCR. + * + * To avoid having to transfer exception bits around, we simply + * say that the FPSCR cumulative exception flags are the logical + * OR of the flags in the two fp statuses. This relies on the + * only thing which needs to read the exception flags being + * an explicit FPSCR read. + */ float_status fp_status; + float_status standard_fp_status; } vfp; uint32_t exclusive_addr; uint32_t exclusive_val; diff --git a/target-arm/helper.c b/target-arm/helper.c index ac47de0..d779055 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -237,6 +237,9 @@ void cpu_reset(CPUARMState *env) env->vfp.xregs[ARM_VFP_FPEXC] = 0; env->cp15.c2_base_mask = 0xffffc000u; #endif + set_flush_to_zero(1, &env->vfp.standard_fp_status); + set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); + set_default_nan_mode(1, &env->vfp.standard_fp_status); tlb_flush(env, 1); } @@ -2256,6 +2259,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUState *env) | (env->vfp.vec_len << 16) | (env->vfp.vec_stride << 20); i = get_float_exception_flags(&env->vfp.fp_status); + i |= get_float_exception_flags(&env->vfp.standard_fp_status); fpscr |= vfp_exceptbits_from_host(i); return fpscr; } @@ -2323,6 +2327,7 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val) i = vfp_exceptbits_to_host(val); set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.standard_fp_status); } void vfp_set_fpscr(CPUState *env, uint32_t val)