From patchwork Thu Nov 11 18:23:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 70851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1A4D2B7139 for ; Fri, 12 Nov 2010 05:25:36 +1100 (EST) Received: from localhost ([127.0.0.1]:50500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGbq0-0005U4-VM for incoming@patchwork.ozlabs.org; Thu, 11 Nov 2010 13:25:33 -0500 Received: from [140.186.70.92] (port=37319 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PGboc-0005RH-BO for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PGboa-0000f8-Tx for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:06 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46368) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PGboa-0000eD-Fc for qemu-devel@nongnu.org; Thu, 11 Nov 2010 13:24:04 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.69) (envelope-from ) id 1PGboY-0007VG-SD for qemu-devel@nongnu.org; Thu, 11 Nov 2010 18:24:02 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 11 Nov 2010 18:23:55 +0000 Message-Id: <1289499842-28818-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1289499842-28818-1-git-send-email-peter.maydell@linaro.org> References: <1289499842-28818-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH 1/8] ARM: Fix decoding of VFP forms of VCVT between float and int/fixed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Correct the decoding of source and destination registers for the VFP forms of the VCVT instructions which convert between floating point and integer or fixed-point. Signed-off-by: Peter Maydell Reviewed-by: Nathan Froyd --- target-arm/translate.c | 19 ++++++++++++------- 1 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 99464ab..0c8439a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2870,16 +2870,18 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) VFP_DREG_N(rn, insn); } - if (op == 15 && (rn == 15 || rn > 17)) { + if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) { /* Integer or single precision destination. */ rd = VFP_SREG_D(insn); } else { VFP_DREG_D(rd, insn); } - - if (op == 15 && (rn == 16 || rn == 17)) { - /* Integer source. */ - rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1); + if (op == 15 && + (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) { + /* VCVT from int is always from S reg regardless of dp bit. + * VCVT with immediate frac_bits has same format as SREG_M + */ + rm = VFP_SREG_M(insn); } else { VFP_DREG_M(rm, insn); } @@ -2891,6 +2893,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) } else { rd = VFP_SREG_D(insn); } + /* NB that we implicitly rely on the encoding for the frac_bits + * in VCVT of fixed to float being the same as that of an SREG_M. + */ rm = VFP_SREG_M(insn); } @@ -3179,8 +3184,8 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) /* Write back the result. */ if (op == 15 && (rn >= 8 && rn <= 11)) ; /* Comparison, do nothing. */ - else if (op == 15 && rn > 17) - /* Integer result. */ + else if (op == 15 && dp && ((rn & 0x1c) == 0x18)) + /* VCVT double to int: always integer result. */ gen_mov_vreg_F0(0, rd); else if (op == 15 && rn == 15) /* conversion */