@@ -2877,7 +2877,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
VFP_DREG_D(rd, insn);
}
- if (op == 15 && (rn == 16 || rn == 17)) {
+ if (op == 15 && ((rn & 0x14) == 0x14)) {
/* Integer source. */
rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
} else {
@@ -3179,7 +3179,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
/* Write back the result. */
if (op == 15 && (rn >= 8 && rn <= 11))
; /* Comparison, do nothing. */
- else if (op == 15 && rn > 17)
+ else if (op == 15 && rn > 17 && ((rn & 0x14) != 0x14))
/* Integer result. */
gen_mov_vreg_F0(0, rd);
else if (op == 15 && rn == 15)
There were two problems with VCVT fixpoint conversion. The most grave was that the micro-ops sequence generated by the instruction triggered a failed assertion in tcg. The second problem was that the extraction of the fraction field from the opcode was erroneous. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> --- target-arm/translate.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)