From patchwork Tue Aug 3 18:14:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matt.waddel@linaro.org X-Patchwork-Id: 60784 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 39C6EB6EF0 for ; Wed, 4 Aug 2010 04:15:41 +1000 (EST) Received: from localhost ([127.0.0.1]:57874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OgM1Y-000517-HM for incoming@patchwork.ozlabs.org; Tue, 03 Aug 2010 14:15:36 -0400 Received: from [140.186.70.92] (port=40978 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OgM13-00050o-LL for qemu-devel@nongnu.org; Tue, 03 Aug 2010 14:15:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OgM11-0001Bq-HL for qemu-devel@nongnu.org; Tue, 03 Aug 2010 14:15:05 -0400 Received: from mail-gy0-f173.google.com ([209.85.160.173]:47194) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OgM11-0001BX-Ey for qemu-devel@nongnu.org; Tue, 03 Aug 2010 14:15:03 -0400 Received: by gyd10 with SMTP id 10so1877124gyd.4 for ; Tue, 03 Aug 2010 11:15:02 -0700 (PDT) Received: by 10.101.28.11 with SMTP id f11mr8517281anj.264.1280859302012; Tue, 03 Aug 2010 11:15:02 -0700 (PDT) Received: from localhost.localdomain (75-162-181-248.slkc.qwest.net [75.162.181.248]) by mx.google.com with ESMTPS id a12sm12189314and.36.2010.08.03.11.15.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 03 Aug 2010 11:15:01 -0700 (PDT) From: matt.waddel@linaro.org To: qemu-devel@nongnu.org Date: Tue, 3 Aug 2010 12:14:50 -0600 Message-Id: <1280859290-25983-1-git-send-email-matt.waddel@linaro.org> X-Mailer: git-send-email 1.7.0.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: Matt Waddel Subject: [Qemu-devel] [PATCH 1/1] Added PMCR support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Matt Waddel Added support for the CP15c9-CR12 register(Performance Monitor Control Register). Calls to this register are being implemented in the ARM Linux kernel. The register has several bit fields, as described in the ARM technical reference manual, but right now I only implemented it as a single register. Signed-off-by: Matt Waddel --- target-arm/cpu.h | 3 ++- target-arm/helper.c | 20 ++++++++++++++++++++ target-arm/machine.c | 2 ++ 3 files changed, 24 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 39c4a0e..a96c512 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -126,6 +126,7 @@ typedef struct CPUARMState { uint32_t c6_data; uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; + uint32_t c9_pmcr; /* Performance Monitor Control Register */ uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_context; /* Context ID. */ uint32_t c13_tls1; /* User RW Thread register. */ @@ -414,7 +415,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 2 +#define CPU_SAVE_VERSION 3 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/helper.c b/target-arm/helper.c index 2dd64d9..2272e8c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1484,6 +1484,16 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) case 1: /* TCM memory region registers. */ /* Not implemented. */ goto bad_reg; + case 12: /* PM control register */ + switch (op2) { + case 0: + /* c9_pmcr register has several bit-fields */ + env->cp15.c9_pmcr = val; + break; + default: + goto bad_reg; + } + break; default: goto bad_reg; } @@ -1774,6 +1784,16 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) goto bad_reg; /* L2 Lockdown and Auxiliary control. */ return 0; + case 12: /* PM control register */ + switch (op2) { + case 0: + /* c9_pmcr register has several bit-fields */ + return env->cp15.c9_pmcr; + break; + default: + goto bad_reg; + } + break; default: goto bad_reg; } diff --git a/target-arm/machine.c b/target-arm/machine.c index 3925d3a..efe9a02 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -43,6 +43,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->cp15.c6_data); qemu_put_be32(f, env->cp15.c9_insn); qemu_put_be32(f, env->cp15.c9_data); + qemu_put_be32(f, env->cp15.c9_pmcr); qemu_put_be32(f, env->cp15.c13_fcse); qemu_put_be32(f, env->cp15.c13_context); qemu_put_be32(f, env->cp15.c13_tls1); @@ -150,6 +151,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->cp15.c6_data = qemu_get_be32(f); env->cp15.c9_insn = qemu_get_be32(f); env->cp15.c9_data = qemu_get_be32(f); + env->cp15.c9_pmcr = qemu_get_be32(f); env->cp15.c13_fcse = qemu_get_be32(f); env->cp15.c13_context = qemu_get_be32(f); env->cp15.c13_tls1 = qemu_get_be32(f);